From 9c29a0dd8c6eae77f3d0addac78331d1a516dc39 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 24 Mar 2025 19:02:36 +0530 Subject: [PATCH 01/16] drm/i915/display: Move intel_psr_post_plane_update() at the later MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit In intel_post_plane_update() there are things which might need to do vblank waits, so enabling PSR as early as we do now is simply counter-productive. Therefore move intel_psr_post_plane_update() at the last of intel_post_plane_update(). Signed-off-by: Ankit Nautiyal Suggested-by: Ville Syrjälä Reviewed-by: Jouni Högander Link: https://lore.kernel.org/r/20250324133248.4071909-5-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ecd2ea00e7fd..0410151a696c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1049,8 +1049,6 @@ static void intel_post_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - intel_psr_post_plane_update(state, crtc); - intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) @@ -1079,6 +1077,8 @@ static void intel_post_plane_update(struct intel_atomic_state *state, if (audio_enabling(old_crtc_state, new_crtc_state)) intel_encoders_audio_enable(state, crtc); + + intel_psr_post_plane_update(state, crtc); } static void intel_post_plane_update_after_readout(struct intel_atomic_state *state, -- 2.51.0 From 660d1c6385b96c3985010589382c9c7849d4734c Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 24 Mar 2025 19:02:37 +0530 Subject: [PATCH 02/16] drm/i915/vrr: Refactor condition for computing vmax and LRR MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit LRR and Vmax can be computed only if VRR is supported and vrr.in_range is set. Currently we proceed with vrr timings only for VRR supporting panels and return otherwise. For using VRR TG with fix timings, need to continue even for panels that do not support VRR. To achieve this, refactor the condition for computing vmax and update_lrr so that we can continue for fixed timings for panels that do not support VRR. v2: Set vmax = vmin for non VRR panels. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/20250324133248.4071909-6-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index c682c487eb25..e68c13ae21b3 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -365,14 +365,16 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->vrr.in_range = intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)); - if (!crtc_state->vrr.in_range) - return; - - if (HAS_LRR(display)) - crtc_state->update_lrr = true; vmin = intel_vrr_compute_vmin(crtc_state); - vmax = intel_vrr_compute_vmax(connector, adjusted_mode); + + if (crtc_state->vrr.in_range) { + if (HAS_LRR(display)) + crtc_state->update_lrr = true; + vmax = intel_vrr_compute_vmax(connector, adjusted_mode); + } else { + vmax = vmin; + } if (vmin >= vmax) return; -- 2.51.0 From be7f2ef5355370d0659b40f5a425af0f310e369a Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 24 Mar 2025 19:02:38 +0530 Subject: [PATCH 03/16] drm/i915/vrr: Always set vrr vmax/vmin/flipline in vrr_{enable/disable} MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit For platforms for which vrr timing generator is always set, VRR_CTL enable bit does not need to toggle, so modify the vrr_{enable/disable} for this. At the moment the helper intel_vrr_always_use_vrr_tg() return false for all cases. This will be set later when all other bits are in place. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/20250324133248.4071909-7-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 40 ++++++++++++++++-------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index e68c13ae21b3..8ae279f132fd 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -560,6 +560,16 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; } +static +bool intel_vrr_always_use_vrr_tg(struct intel_display *display) +{ + if (!HAS_VRR(display)) + return false; + + /* #TODO return true for platforms supporting fixed_rr */ + return false; +} + void intel_vrr_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -578,13 +588,15 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN); - if (crtc_state->cmrr.enable) { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | - trans_vrr_ctl(crtc_state)); - } else { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (!intel_vrr_always_use_vrr_tg(display)) { + if (crtc_state->cmrr.enable) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } else { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } } } @@ -596,12 +608,14 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) if (!old_crtc_state->vrr.enable) return; - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - trans_vrr_ctl(old_crtc_state)); - intel_de_wait_for_clear(display, - TRANS_VRR_STATUS(display, cpu_transcoder), - VRR_STATUS_VRR_EN_LIVE, 1000); - intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); + if (!intel_vrr_always_use_vrr_tg(display)) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(old_crtc_state)); + intel_de_wait_for_clear(display, + TRANS_VRR_STATUS(display, cpu_transcoder), + VRR_STATUS_VRR_EN_LIVE, 1000); + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); + } intel_vrr_set_fixed_rr_timings(old_crtc_state); } -- 2.51.0 From 1d46cee7b6e4dad25c2621aa2a3ac325500ed620 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 24 Mar 2025 19:02:39 +0530 Subject: [PATCH 04/16] drm/i915/vrr: Set vrr.enable for VRR TG with fixed_rr MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit For platforms that enable VRR TG only for variable timings, the VRR_CTL.VRR_ENABLE bit indicates VRR is active. For platforms that always have VRR TG enabled, the VRR_CTL.VRR_ENABLE bit indicates VRR is active only when not in fixed refresh rate mode. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/20250324133248.4071909-8-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 8ae279f132fd..8a0d27666ea7 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -632,6 +632,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 trans_vrr_ctl, trans_vrr_vsync; + bool vrr_enable; trans_vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); @@ -675,7 +676,12 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) } } - crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + vrr_enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + + if (intel_vrr_always_use_vrr_tg(display)) + crtc_state->vrr.enable = vrr_enable && !intel_vrr_is_fixed_rr(crtc_state); + else + crtc_state->vrr.enable = vrr_enable; /* * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags. -- 2.51.0 From 7895991a29942b7843b14074e661830cb37e6e95 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 24 Mar 2025 19:02:40 +0530 Subject: [PATCH 05/16] drm/i915/display: Use fixed_rr timings in modeset sequence MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit During modeset enable sequence, program the fixed timings, and turn on the VRR Timing Generator (VRR TG) for platforms that always use VRR TG. For this intel_vrr_set_transcoder now always programs fixed timings. Later if vrr timings are required, vrr_enable() will switch to the real VRR timings. For platforms that will always use VRR TG, the VRR_CTL Enable bit is set and reset in the transcoder enable/disable path. v2: Update intel_vrr_set_transcoder_timings for fixed_rr. v3: Update intel_set_transcoder_timings_lrr for fixed_rr. (Ville) v4: Have separate functions to enable/disable VRR CTL v5: -For platforms that do not always have VRRTG on, do write bits other than enable bit and also use write the TRANS_VRR_PUSH register. (Ville) -Avoid writing trans_ctl_vrr if !vrr_possible(). v6: -Disable VRR just before intel_ddi_disable_transcoder_func(). (Ville) -Correct the sequence of configuring PUSH and VRR Enable/Disable. (Ville) v7: Reset trans_vrr_ctl to 0 unconditionally in intel_vrr_transcoder_disable(). (Ville) v8: Reset trans_vrr_ctl if flipline is not set. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/20250324133248.4071909-9-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++ drivers/gpu/drm/i915/display/intel_vrr.c | 51 +++++++++++++++++---- drivers/gpu/drm/i915/display/intel_vrr.h | 2 + 4 files changed, 54 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index f38c998935b9..44f4465c27e2 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -78,6 +78,7 @@ #include "intel_tc.h" #include "intel_vdsc.h" #include "intel_vdsc_regs.h" +#include "intel_vrr.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -3249,6 +3250,8 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); } + intel_vrr_transcoder_disable(old_crtc_state); + intel_ddi_disable_transcoder_func(old_crtc_state); for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { @@ -3522,6 +3525,8 @@ static void intel_ddi_enable(struct intel_atomic_state *state, intel_ddi_enable_transcoder_func(encoder, crtc_state); + intel_vrr_transcoder_enable(crtc_state); + /* Enable/Disable DP2.0 SDP split config before transcoder */ intel_audio_sdp_split_update(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index bd47cf127b4c..d2988b9a6e7b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1065,6 +1065,8 @@ static void mst_stream_post_disable(struct intel_atomic_state *state, drm_dp_remove_payload_part2(&intel_dp->mst.mgr, new_mst_state, old_payload, new_payload); + intel_vrr_transcoder_disable(old_crtc_state); + intel_ddi_disable_transcoder_func(old_crtc_state); for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { @@ -1326,6 +1328,8 @@ static void mst_stream_enable(struct intel_atomic_state *state, intel_ddi_enable_transcoder_func(encoder, pipe_config); + intel_vrr_transcoder_enable(pipe_config); + intel_ddi_clear_act_sent(encoder, pipe_config); intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), 0, diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 8a0d27666ea7..96b6b730bea4 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -479,14 +479,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) lower_32_bits(crtc_state->cmrr.cmrr_n)); } - intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), - crtc_state->vrr.vmin - 1); - intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), - crtc_state->vrr.vmax - 1); - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - trans_vrr_ctl(crtc_state)); - intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), - crtc_state->vrr.flipline - 1); + intel_vrr_set_fixed_rr_timings(crtc_state); if (HAS_AS_SDP(display)) intel_de_write(display, @@ -620,6 +613,48 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) intel_vrr_set_fixed_rr_timings(old_crtc_state); } +void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!HAS_VRR(display)) + return; + + if (!intel_vrr_possible(crtc_state)) + return; + + if (!intel_vrr_always_use_vrr_tg(display)) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(crtc_state)); + return; + } + + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), + TRANS_PUSH_EN); + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); +} + +void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!HAS_VRR(display)) + return; + + if (!intel_vrr_possible(crtc_state)) + return; + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 0); + + intel_de_wait_for_clear(display, TRANS_VRR_STATUS(display, cpu_transcoder), + VRR_STATUS_VRR_EN_LIVE, 1000); + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); +} + bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state) { return crtc_state->vrr.flipline && diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 65d2b0eead51..859f1dc8a6d7 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -36,5 +36,7 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state); bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state); +void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); +void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ -- 2.51.0 From dda7dcd9da73c5327aef42b89f0519bb51e84217 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 24 Mar 2025 19:02:41 +0530 Subject: [PATCH 06/16] drm/i915/vrr: Use fixed timings for platforms that support VRR MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit For fixed refresh rate use fixed timings for all platforms that support VRR. For this add checks to avoid computing and reading VRR for platforms that do not support VRR. v2: Avoid touching check for VRR_CTL_FLIP_LINE_EN. (Ville) v3: Avoid redundant statements in vrr_{compute/get}_config. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/20250324133248.4071909-10-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 96b6b730bea4..f225fd7f34ff 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -353,6 +353,9 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int vmin, vmax; + if (!HAS_VRR(display)) + return; + /* * FIXME all joined pipes share the same transcoder. * Need to account for that during VRR toggle/push/etc. @@ -376,15 +379,12 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, vmax = vmin; } - if (vmin >= vmax) - return; - crtc_state->vrr.vmin = vmin; crtc_state->vrr.vmax = vmax; crtc_state->vrr.flipline = crtc_state->vrr.vmin; - if (crtc_state->uapi.vrr_enabled) + if (crtc_state->uapi.vrr_enabled && vmin < vmax) intel_vrr_compute_vrr_timings(crtc_state); else if (is_cmrr_frac_required(crtc_state) && is_edp) intel_vrr_compute_cmrr_timings(crtc_state); -- 2.51.0 From 704bd24d010e1491bc63b738145be4827e235e22 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 24 Mar 2025 19:02:42 +0530 Subject: [PATCH 07/16] drm/i915/display: Use fixed rr timings in intel_set_transcoder_timings_lrr() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Update the intel_set_transcoder_timings_lrr() function to use fixed refresh rate timings. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/20250324133248.4071909-11-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/display/intel_vrr.c | 1 - drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0410151a696c..5713a4d017d7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2768,6 +2768,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); + + intel_vrr_set_fixed_rr_timings(crtc_state); + intel_vrr_transcoder_enable(crtc_state); } static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index f225fd7f34ff..352b853c10eb 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -286,7 +286,6 @@ int intel_vrr_fixed_rr_flipline(const struct intel_crtc_state *crtc_state) return intel_vrr_fixed_rr_vtotal(crtc_state); } -static void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 859f1dc8a6d7..c95acf1ad238 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -38,5 +38,6 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state); bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); +void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ -- 2.51.0 From 423f9d7c52235a7b63f5b03655a722ee3c1cdb24 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 24 Mar 2025 19:02:43 +0530 Subject: [PATCH 08/16] drm/i915/display: Move vrr.guardband/pipeline_full out of !fastset block MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Since the vrr.guardband can now change for platforms that always use the VRR Timing Generator, and it is unsafe to reprogram the guardband on the fly, move the guardband and pipeline_full checks from the pure !fastboot path and add a check for intel_vrr_always_use_vrr_tg(). For older platforms the vrr.guardband change happens when VRR Timing generator is off. For the platforms that always use the VRR Timing Generator, this will prevent reprogramming the vrr.guardband without a full modeset. However, this will disrupt LRR functionality for these platforms. v2: Modify the check to avoid breaking the LRR on older platform. (Ville) v3: Correct the oversight of not removing the lines from the original location. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/20250324133248.4071909-12-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++++-- drivers/gpu/drm/i915/display/intel_vrr.c | 1 - drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++ 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 5713a4d017d7..a2e6c01beeb5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5387,8 +5387,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.vmin); PIPE_CONF_CHECK_I(vrr.vmax); PIPE_CONF_CHECK_I(vrr.flipline); - PIPE_CONF_CHECK_I(vrr.pipeline_full); - PIPE_CONF_CHECK_I(vrr.guardband); PIPE_CONF_CHECK_I(vrr.vsync_start); PIPE_CONF_CHECK_I(vrr.vsync_end); PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); @@ -5396,6 +5394,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(cmrr.enable); } + if (!fastset || intel_vrr_always_use_vrr_tg(display)) { + PIPE_CONF_CHECK_I(vrr.pipeline_full); + PIPE_CONF_CHECK_I(vrr.guardband); + } + #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_LLI diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 352b853c10eb..c57e0319d83c 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -552,7 +552,6 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; } -static bool intel_vrr_always_use_vrr_tg(struct intel_display *display) { if (!HAS_VRR(display)) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index c95acf1ad238..38bf9996b883 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -13,6 +13,7 @@ struct intel_atomic_state; struct intel_connector; struct intel_crtc_state; struct intel_dsb; +struct intel_display; bool intel_vrr_is_capable(struct intel_connector *connector); bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh); @@ -39,5 +40,6 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); +bool intel_vrr_always_use_vrr_tg(struct intel_display *display); #endif /* __INTEL_VRR_H__ */ -- 2.51.0 From 0ec46988ae6c5f3e6c4ccdf5e0abbc541b8d0680 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 24 Mar 2025 19:02:44 +0530 Subject: [PATCH 09/16] drm/i915/vrr: Allow fixed_rr with pipe joiner MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit VRR with joiner is currently disabled as it still needs some work to correctly sequence the primary and secondary transcoders. However, we can still use VRR Timing generator in fixed refresh rate for joiner and since it just need to program vrr timings once and does not involve changing timings on the fly. We still need to skip the VRR and LRR for joiner. To achieve this set vrr.in_range to 0 for joiner case, so that we do not try VRR and LRR for the joiner case. v2: Avoid checks for secondary pipes, where not required. (Ville) v3: Remove a redundant check and reset vrr.in_range to false. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/20250324133248.4071909-13-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index c57e0319d83c..dda42522f461 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -355,19 +355,23 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, if (!HAS_VRR(display)) return; - /* - * FIXME all joined pipes share the same transcoder. - * Need to account for that during VRR toggle/push/etc. - */ - if (crtc_state->joiner_pipes) - return; - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) return; crtc_state->vrr.in_range = intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)); + /* + * Allow fixed refresh rate with VRR Timing Generator. + * For now set the vrr.in_range to 0, to allow fixed_rr but skip actual + * VRR and LRR. + * #TODO For actual VRR with joiner, we need to figure out how to + * correctly sequence transcoder level stuff vs. pipe level stuff + * in the commit. + */ + if (crtc_state->joiner_pipes) + crtc_state->vrr.in_range = false; + vmin = intel_vrr_compute_vmin(crtc_state); if (crtc_state->vrr.in_range) { -- 2.51.0 From cfd51309f8c89594ceac7d084c1e4eb4fbf9f142 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 24 Mar 2025 19:02:45 +0530 Subject: [PATCH 10/16] drm/i915/vrr: Always use VRR timing generator for PTL+ MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Currently, the VRR timing generator is used only when VRR is enabled by userspace for sinks that support VRR. Starting with PTL+, gradually move away from the legacy timing generator and use the VRR timing generator for both variable and fixed timings. Note: For platforms where we always enable the VRR timing generator, the LRR fastset is not allowed to avoid live programming of vrr.guardband with VRR TG enabled. This effectively breaks the LRR fastset functionality for these platforms and needs to be addressed. v2: Use this for PTL for now to avoid losing LRR fastset for older platforms. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/20250324133248.4071909-14-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index dda42522f461..5e60da2bb0c3 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -561,7 +561,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display) if (!HAS_VRR(display)) return false; - /* #TODO return true for platforms supporting fixed_rr */ + if (DISPLAY_VER(display) >= 30) + return true; + return false; } -- 2.51.0 From e2b1dd430d3643842990589302c61c7d6ec4115e Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 24 Mar 2025 19:02:46 +0530 Subject: [PATCH 11/16] drm/i915/vrr: Set trans_vrr_ctl in intel_vrr_set_transcoder_timings() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit We now always set vrr.flipline, vmin, and vmax for all platforms that support VRR. Therefore, we should set all TRANS_VRR_CTL bits except VRR_ENABLE. Without this, the readback for these bits will fail because we only read vrr.flipline, vmin, and vmax if TRANS_VRR_CTL has the FLIPLINE_EN bit set. For platforms that always have the VRR Timing Generator enabled, the FLIPLINE_EN bit is always set in TRANS_VRR_CTL during intel_transcoder_vrr_enable(). However, for the remaining platforms (that do not always have the VRR Timing Generator enabled) if a full modeset doesn't occur and VRR is not enabled, the bit is not set. This results in a mismatch between the software state and hardware state because the software state expects VRR timings like flipline, vmin, and vmax to be set, but the readout for these doesn't happen since the FLIPLINE_EN bit is not set in TRANS_VRR_CTL. To avoid this mismatch, write trans_vrr_ctl in intel_vrr_set_transcoder_timings() even when VRR is not enabled for platforms that do not have the VRR Timing Generator always enabled. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/20250324133248.4071909-15-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 5e60da2bb0c3..414f93851059 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -484,6 +484,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) intel_vrr_set_fixed_rr_timings(crtc_state); + if (!intel_vrr_always_use_vrr_tg(display) && !crtc_state->vrr.enable) + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(crtc_state)); + if (HAS_AS_SDP(display)) intel_de_write(display, TRANS_VRR_VSYNC(display, cpu_transcoder), -- 2.51.0 From 7ab420b966346067132b05be8196e67adc72e568 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Mon, 10 Mar 2025 20:35:27 +0200 Subject: [PATCH 12/16] drm/i915: Enable/disable shared dplls just the once for joined pipes MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Currently we loop over all joined pipes and enable/disable the shared dplls for each. We don't really have to do that since all joined pipes will be using the same dpll. So let's just do the enable/disable once for the whole set of joined pipes. We can still keep tracking the dpll active set as pipes as long as we remember to flip the bits for all the joined pipes on one go. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250310183528.3203-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 16 +++------------- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 ++-- 2 files changed, 5 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a2e6c01beeb5..526074ed5026 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1661,13 +1661,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_encoders_pre_pll_enable(state, crtc); - for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { - const struct intel_crtc_state *pipe_crtc_state = - intel_atomic_get_new_crtc_state(state, pipe_crtc); - - if (pipe_crtc_state->shared_dpll) - intel_enable_shared_dpll(pipe_crtc_state); - } + if (new_crtc_state->shared_dpll) + intel_enable_shared_dpll(new_crtc_state); intel_encoders_pre_enable(state, crtc); @@ -1798,12 +1793,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, intel_encoders_disable(state, crtc); intel_encoders_post_disable(state, crtc); - for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { - const struct intel_crtc_state *old_pipe_crtc_state = - intel_atomic_get_old_crtc_state(state, pipe_crtc); - - intel_disable_shared_dpll(old_pipe_crtc_state); - } + intel_disable_shared_dpll(old_crtc_state); intel_encoders_post_pll_disable(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 953cac2bd1dc..ec7feef1ef59 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -257,7 +257,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_shared_dpll *pll = crtc_state->shared_dpll; - unsigned int pipe_mask = BIT(crtc->pipe); + unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state); unsigned int old_mask; if (drm_WARN_ON(display->drm, !pll)) @@ -303,7 +303,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_shared_dpll *pll = crtc_state->shared_dpll; - unsigned int pipe_mask = BIT(crtc->pipe); + unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state); /* PCH only available on ILK+ */ if (DISPLAY_VER(display) < 5) -- 2.51.0 From e8828d7fdbb9241d44f9c403f5088e05b3da102c Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Mon, 10 Mar 2025 20:35:28 +0200 Subject: [PATCH 13/16] drm/i915: Move intel_disable_shared_dpll() into ilk_pch_post_disable() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit On ILK-IVB only PCH outputs use shared dplls. Move the relevant intel_disable_shared_dpll() into ilk_pch_post_disable() to make that clear (and if we extend the dpll mgr to cover all plls we need different enable/disable points anyway for the PCH vs. CPU eDP cases). The intel_enable_shared_dpll() counterpart was already in ilk_pch_enable() anyway, so this is the more symmetric place for the disable as well. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250310183528.3203-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 2 -- drivers/gpu/drm/i915/display/intel_pch_display.c | 4 ++++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 526074ed5026..ee7812126129 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1773,8 +1773,6 @@ static void ilk_crtc_disable(struct intel_atomic_state *state, intel_set_cpu_fifo_underrun_reporting(display, pipe, true); intel_set_pch_fifo_underrun_reporting(display, pipe, true); - - intel_disable_shared_dpll(old_crtc_state); } static void hsw_crtc_disable(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 27fb386c84c3..b909ed18a5b2 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -460,6 +460,8 @@ void ilk_pch_post_disable(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; ilk_disable_pch_transcoder(crtc); @@ -476,6 +478,8 @@ void ilk_pch_post_disable(struct intel_atomic_state *state, } ilk_fdi_pll_disable(crtc); + + intel_disable_shared_dpll(old_crtc_state); } static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) -- 2.51.0 From 1ca3991f6400769427bf1a5ff55def328612a947 Mon Sep 17 00:00:00 2001 From: William Tseng Date: Tue, 11 Mar 2025 18:06:26 +0800 Subject: [PATCH 14/16] drm/i915/dsi: let HW maintain the HS-TRAIL timing This change is to avoid over-specification of the TEOT timing parameter, which is derived from software in current design. Supposed that THS-TRAIL and THS-EXIT have the minimum values, i.e., 60 and 100 in ns. If SW is overriding the HW default, the TEOT value becomes 150 ns, approximately calculated by the following formula. DIV_ROUND_UP(60/50)*50 + DIV_ROUND_UP(100/50))*50/2, where 50 is LP Escape Clock time in ns. The TEOT value 150 ns is larger than the maximum value, around 136 ns if UI is 1.8ns, (105 ns + 12*UI, defined by MIPI DPHY specification). However, the TEOT value will meet the specification if THS-TRAIL is set to the HW default, instead of software overriding. The timing change is made for both data lane and clock lane. v1: initial version. v2: change clock lane dphy timings. v3: remove calculation of trail cnt. v4: rebase. Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13891 Cc: Ville Syrjala Cc: Jani Nikula Cc: Vandita Kulkarni Cc: Lee Shawn C Cc: Cooper Chiou Signed-off-by: William Tseng Acked-by: Vandita Kulkarni Link: https://lore.kernel.org/r/20250311100626.533888-1-william.tseng@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 402b7b2e1829..ef9a9d780bfc 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1840,14 +1840,13 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) struct intel_connector *connector = intel_dsi->attached_connector; struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; u32 tlpx_ns; - u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; - u32 ths_prepare_ns, tclk_trail_ns; + u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt; + u32 ths_prepare_ns; u32 hs_zero_cnt; u32 tclk_pre_cnt; tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); - tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); ths_prepare_ns = max(mipi_config->ths_prepare, mipi_config->tclk_prepare); @@ -1874,14 +1873,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; } - /* trail cnt in escape clocks*/ - trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); - if (trail_cnt > ICL_TRAIL_CNT_MAX) { - drm_dbg_kms(display->drm, "trail_cnt out of range (%d)\n", - trail_cnt); - trail_cnt = ICL_TRAIL_CNT_MAX; - } - /* tclk pre count in escape clocks */ tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { @@ -1914,17 +1905,13 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) CLK_ZERO_OVERRIDE | CLK_ZERO(clk_zero_cnt) | CLK_PRE_OVERRIDE | - CLK_PRE(tclk_pre_cnt) | - CLK_TRAIL_OVERRIDE | - CLK_TRAIL(trail_cnt)); + CLK_PRE(tclk_pre_cnt)); /* data lanes dphy timings */ intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | HS_PREPARE(prepare_cnt) | HS_ZERO_OVERRIDE | HS_ZERO(hs_zero_cnt) | - HS_TRAIL_OVERRIDE | - HS_TRAIL(trail_cnt) | HS_EXIT_OVERRIDE | HS_EXIT(exit_zero_cnt)); -- 2.51.0 From f9f4ffa84252f677b4c3fd0c1c28a2fe4f4b7b59 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 25 Mar 2025 14:36:33 +0200 Subject: [PATCH 15/16] drm/i915/dpll: convert intel_dpll.[ch] to struct intel_display MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Going forward, struct intel_display is the main display device data pointer. Convert as much as possible of intel_dpll.[ch] to struct intel_display. Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/16fe331ba51c269d6f9871d7b0a3b8df3c7b5342.1742906146.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 4 +- .../drm/i915/display/intel_display_driver.c | 4 +- drivers/gpu/drm/i915/display/intel_dpll.c | 312 +++++++++--------- drivers/gpu/drm/i915/display/intel_dpll.h | 13 +- drivers/gpu/drm/i915/display/intel_pps.c | 5 +- 5 files changed, 160 insertions(+), 178 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ee7812126129..103173836abf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2134,9 +2134,9 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state, if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { if (display->platform.cherryview) - chv_disable_pll(dev_priv, pipe); + chv_disable_pll(display, pipe); else if (display->platform.valleyview) - vlv_disable_pll(dev_priv, pipe); + vlv_disable_pll(display, pipe); else i9xx_disable_pll(old_crtc_state); } diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index e4fbf1e5b2bb..61748525da0b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -181,8 +181,6 @@ static void intel_plane_possible_crtcs_init(struct intel_display *display) void intel_display_driver_early_probe(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (!HAS_DISPLAY(display)) return; @@ -198,7 +196,7 @@ void intel_display_driver_early_probe(struct intel_display *display) intel_color_init_hooks(display); intel_init_cdclk_hooks(display); intel_audio_hooks_init(display); - intel_dpll_init_clock_hook(i915); + intel_dpll_init_clock_hook(display); intel_init_display_hooks(display); intel_fdi_init_hook(display); intel_dmc_wl_init(display); diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 23f4e01c3e8f..0481b1365b85 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -373,14 +373,15 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock) static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) - return i915->display.vbt.lvds_ssc_freq; + return display->vbt.lvds_ssc_freq; else if (HAS_PCH_SPLIT(i915)) return 120000; - else if (DISPLAY_VER(i915) != 2) + else if (DISPLAY_VER(display) != 2) return 96000; else return 48000; @@ -389,27 +390,27 @@ static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state) void i9xx_dpll_get_hw_state(struct intel_crtc *crtc, struct intel_dpll_hw_state *dpll_hw_state) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; - if (DISPLAY_VER(dev_priv) >= 4) { + if (DISPLAY_VER(display) >= 4) { u32 tmp; /* No way to read it out on pipes B and C */ - if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) - tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; + if (display->platform.cherryview && crtc->pipe != PIPE_A) + tmp = display->state.chv_dpll_md[crtc->pipe]; else - tmp = intel_de_read(dev_priv, - DPLL_MD(dev_priv, crtc->pipe)); + tmp = intel_de_read(display, + DPLL_MD(display, crtc->pipe)); hw_state->dpll_md = tmp; } - hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe)); + hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe)); - if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { - hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe)); - hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe)); + if (!display->platform.valleyview && !display->platform.cherryview) { + hw_state->fp0 = intel_de_read(display, FP0(crtc->pipe)); + hw_state->fp1 = intel_de_read(display, FP1(crtc->pipe)); } else { /* Mask out read-only status bits. */ hw_state->dpll &= ~(DPLL_LOCK_VLV | @@ -423,7 +424,6 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; u32 dpll = hw_state->dpll; u32 fp; @@ -437,7 +437,7 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state) fp = hw_state->fp1; clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; - if (IS_PINEVIEW(dev_priv)) { + if (display->platform.pineview) { clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; } else { @@ -445,8 +445,8 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state) clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; } - if (DISPLAY_VER(dev_priv) != 2) { - if (IS_PINEVIEW(dev_priv)) + if (DISPLAY_VER(display) != 2) { + if (display->platform.pineview) clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); else @@ -463,23 +463,23 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state) 7 : 14; break; default: - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Unknown DPLL mode %08x in programmed " "mode\n", (int)(dpll & DPLL_MODE_MASK)); return; } - if (IS_PINEVIEW(dev_priv)) + if (display->platform.pineview) port_clock = pnv_calc_dpll_params(refclk, &clock); else port_clock = i9xx_calc_dpll_params(refclk, &clock); } else { enum pipe lvds_pipe; - if (IS_I85X(dev_priv) && + if (display->platform.i85x && intel_lvds_port_enabled(display, LVDS, &lvds_pipe) && lvds_pipe == crtc->pipe) { - u32 lvds = intel_de_read(dev_priv, LVDS); + u32 lvds = intel_de_read(display, LVDS); clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> DPLL_FPA01_P1_POST_DIV_SHIFT); @@ -578,7 +578,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) * Returns whether the given set of divisors are valid for a given refclk with * the given connectors. */ -static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, +static bool intel_pll_is_valid(struct intel_display *display, const struct intel_limit *limit, const struct dpll *clock) { @@ -591,14 +591,14 @@ static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) return false; - if (!IS_PINEVIEW(dev_priv) && - !IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - !IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv)) + if (!display->platform.pineview && + !display->platform.valleyview && !display->platform.cherryview && + !display->platform.broxton && !display->platform.geminilake) if (clock->m1 <= clock->m2) return false; - if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - !IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv)) { + if (!display->platform.valleyview && !display->platform.cherryview && + !display->platform.broxton && !display->platform.geminilake) { if (clock->p < limit->p.min || limit->p.max < clock->p) return false; if (clock->m < limit->m.min || limit->m.max < clock->m) @@ -657,7 +657,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit, const struct dpll *match_clock, struct dpll *best_clock) { - struct drm_device *dev = crtc_state->uapi.crtc->dev; + struct intel_display *display = to_intel_display(crtc_state); struct dpll clock; int err = target; @@ -678,7 +678,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit, int this_err; i9xx_calc_dpll_params(refclk, &clock); - if (!intel_pll_is_valid(to_i915(dev), + if (!intel_pll_is_valid(display, limit, &clock)) continue; @@ -715,7 +715,7 @@ pnv_find_best_dpll(const struct intel_limit *limit, const struct dpll *match_clock, struct dpll *best_clock) { - struct drm_device *dev = crtc_state->uapi.crtc->dev; + struct intel_display *display = to_intel_display(crtc_state); struct dpll clock; int err = target; @@ -734,7 +734,7 @@ pnv_find_best_dpll(const struct intel_limit *limit, int this_err; pnv_calc_dpll_params(refclk, &clock); - if (!intel_pll_is_valid(to_i915(dev), + if (!intel_pll_is_valid(display, limit, &clock)) continue; @@ -771,7 +771,7 @@ g4x_find_best_dpll(const struct intel_limit *limit, const struct dpll *match_clock, struct dpll *best_clock) { - struct drm_device *dev = crtc_state->uapi.crtc->dev; + struct intel_display *display = to_intel_display(crtc_state); struct dpll clock; int max_n; bool found = false; @@ -795,7 +795,7 @@ g4x_find_best_dpll(const struct intel_limit *limit, int this_err; i9xx_calc_dpll_params(refclk, &clock); - if (!intel_pll_is_valid(to_i915(dev), + if (!intel_pll_is_valid(display, limit, &clock)) continue; @@ -818,7 +818,7 @@ g4x_find_best_dpll(const struct intel_limit *limit, * Check if the calculated PLL configuration is more optimal compared to the * best configuration and error found so far. Return the calculated error. */ -static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, +static bool vlv_PLL_is_optimal(struct intel_display *display, int target_freq, const struct dpll *calculated_clock, const struct dpll *best_clock, unsigned int best_error_ppm, @@ -828,13 +828,13 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, * For CHV ignore the error and consider only the P value. * Prefer a bigger P value based on HW requirements. */ - if (IS_CHERRYVIEW(to_i915(dev))) { + if (display->platform.cherryview) { *error_ppm = 0; return calculated_clock->p > best_clock->p; } - if (drm_WARN_ON_ONCE(dev, !target_freq)) + if (drm_WARN_ON_ONCE(display->drm, !target_freq)) return false; *error_ppm = div_u64(1000000ULL * @@ -865,8 +865,7 @@ vlv_find_best_dpll(const struct intel_limit *limit, const struct dpll *match_clock, struct dpll *best_clock) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_device *dev = crtc->base.dev; + struct intel_display *display = to_intel_display(crtc_state); struct dpll clock; unsigned int bestppm = 1000000; /* min update 19.2 MHz */ @@ -890,12 +889,12 @@ vlv_find_best_dpll(const struct intel_limit *limit, vlv_calc_dpll_params(refclk, &clock); - if (!intel_pll_is_valid(to_i915(dev), + if (!intel_pll_is_valid(display, limit, &clock)) continue; - if (!vlv_PLL_is_optimal(dev, target, + if (!vlv_PLL_is_optimal(display, target, &clock, best_clock, bestppm, &ppm)) @@ -923,8 +922,7 @@ chv_find_best_dpll(const struct intel_limit *limit, const struct dpll *match_clock, struct dpll *best_clock) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_device *dev = crtc->base.dev; + struct intel_display *display = to_intel_display(crtc_state); unsigned int best_error_ppm; struct dpll clock; u64 m2; @@ -959,10 +957,10 @@ chv_find_best_dpll(const struct intel_limit *limit, chv_calc_dpll_params(refclk, &clock); - if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) + if (!intel_pll_is_valid(display, limit, &clock)) continue; - if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, + if (!vlv_PLL_is_optimal(display, target, &clock, best_clock, best_error_ppm, &error_ppm)) continue; @@ -1006,8 +1004,6 @@ static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state, const struct dpll *reduced_clock) { struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dpll; dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; @@ -1017,8 +1013,8 @@ static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state, else dpll |= DPLLB_MODE_DAC_SERIAL; - if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || - IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { + if (display->platform.i945g || display->platform.i945gm || + display->platform.g33 || display->platform.pineview) { dpll |= (crtc_state->pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; } @@ -1031,10 +1027,10 @@ static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state, dpll |= DPLL_SDVO_HIGH_SPEED; /* compute bitmask from p1 value */ - if (IS_G4X(dev_priv)) { + if (display->platform.g4x) { dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; - } else if (IS_PINEVIEW(dev_priv)) { + } else if (display->platform.pineview) { dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; WARN_ON(reduced_clock->p1 != clock->p1); } else { @@ -1058,7 +1054,7 @@ static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state, } WARN_ON(reduced_clock->p2 != clock->p2); - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); if (crtc_state->sdvo_tv_clock) @@ -1076,11 +1072,10 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, const struct dpll *clock, const struct dpll *reduced_clock) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; - if (IS_PINEVIEW(dev_priv)) { + if (display->platform.pineview) { hw_state->fp0 = pnv_dpll_compute_fp(clock); hw_state->fp1 = pnv_dpll_compute_fp(reduced_clock); } else { @@ -1090,7 +1085,7 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock); - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) hw_state->dpll_md = i965_dpll_md(crtc_state); } @@ -1099,8 +1094,6 @@ static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state, const struct dpll *reduced_clock) { struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dpll; dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; @@ -1130,7 +1123,7 @@ static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state, * both DPLLS. The spec says we should disable the DVO 2X clock * when not needed, but this seems to work fine in practice. */ - if (IS_I830(dev_priv) || + if (display->platform.i830 || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) dpll |= DPLL_DVO_2X_MODE; @@ -1158,14 +1151,14 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, static int hsw_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_encoder *encoder = intel_get_crtc_new_encoder(state, crtc_state); int ret; - if (DISPLAY_VER(dev_priv) < 11 && + if (DISPLAY_VER(display) < 11 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; @@ -1187,13 +1180,13 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_encoder *encoder = intel_get_crtc_new_encoder(state, crtc_state); - if (DISPLAY_VER(dev_priv) < 11 && + if (DISPLAY_VER(display) < 11 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; @@ -1246,7 +1239,7 @@ static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state) struct drm_i915_private *i915 = to_i915(crtc->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && - ((intel_panel_use_ssc(display) && i915->display.vbt.lvds_ssc_freq == 100000) || + ((intel_panel_use_ssc(display) && display->vbt.lvds_ssc_freq == 100000) || (HAS_PCH_IBX(i915) && intel_is_dual_link_lvds(display)))) return 25; @@ -1277,8 +1270,6 @@ static u32 ilk_dpll(const struct intel_crtc_state *crtc_state, const struct dpll *reduced_clock) { struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dpll; dpll = DPLL_VCO_ENABLE; @@ -1312,7 +1303,7 @@ static u32 ilk_dpll(const struct intel_crtc_state *crtc_state, * clear if it''s a win or loss power wise. No point in doing * this on ILK at all since it has a fixed DPLL<->pipe mapping. */ - if (INTEL_NUM_PIPES(dev_priv) == 3 && + if (INTEL_NUM_PIPES(display) == 3 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) dpll |= DPLL_SDVO_HIGH_SPEED; @@ -1363,7 +1354,6 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_limit *limit; @@ -1376,10 +1366,10 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(display)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "using SSC reference clock of %d kHz\n", - dev_priv->display.vbt.lvds_ssc_freq); - refclk = dev_priv->display.vbt.lvds_ssc_freq; + display->vbt.lvds_ssc_freq); + refclk = display->vbt.lvds_ssc_freq; } if (intel_is_dual_link_lvds(display)) { @@ -1540,7 +1530,6 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_limit *limit; @@ -1548,8 +1537,8 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(display)) { - refclk = dev_priv->display.vbt.lvds_ssc_freq; - drm_dbg_kms(&dev_priv->drm, + refclk = display->vbt.lvds_ssc_freq; + drm_dbg_kms(display->drm, "using SSC reference clock of %d kHz\n", refclk); } @@ -1590,7 +1579,6 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_limit *limit; @@ -1598,8 +1586,8 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(display)) { - refclk = dev_priv->display.vbt.lvds_ssc_freq; - drm_dbg_kms(&dev_priv->drm, + refclk = display->vbt.lvds_ssc_freq; + drm_dbg_kms(display->drm, "using SSC reference clock of %d kHz\n", refclk); } @@ -1629,7 +1617,6 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_limit *limit; @@ -1637,8 +1624,8 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(display)) { - refclk = dev_priv->display.vbt.lvds_ssc_freq; - drm_dbg_kms(&dev_priv->drm, + refclk = display->vbt.lvds_ssc_freq; + drm_dbg_kms(display->drm, "using SSC reference clock of %d kHz\n", refclk); } @@ -1670,7 +1657,6 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_limit *limit; @@ -1678,8 +1664,8 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(display)) { - refclk = dev_priv->display.vbt.lvds_ssc_freq; - drm_dbg_kms(&dev_priv->drm, + refclk = display->vbt.lvds_ssc_freq; + drm_dbg_kms(display->drm, "using SSC reference clock of %d kHz\n", refclk); } @@ -1752,12 +1738,12 @@ static const struct intel_dpll_funcs i8xx_dpll_funcs = { int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); int ret; - drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); + drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state)); memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state)); @@ -1765,9 +1751,9 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, if (!crtc_state->hw.enable) return 0; - ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); + ret = display->funcs.dpll->crtc_compute_clock(state, crtc); if (ret) { - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", crtc->base.base.id, crtc->base.name); return ret; } @@ -1778,23 +1764,23 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); int ret; - drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); - drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); + drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state)); + drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); if (!crtc_state->hw.enable || crtc_state->shared_dpll) return 0; - if (!i915->display.funcs.dpll->crtc_get_shared_dpll) + if (!display->funcs.dpll->crtc_get_shared_dpll) return 0; - ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); + ret = display->funcs.dpll->crtc_get_shared_dpll(state, crtc); if (ret) { - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", crtc->base.base.id, crtc->base.name); return ret; } @@ -1803,43 +1789,44 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, } void -intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) -{ - if (DISPLAY_VER(dev_priv) >= 14) - dev_priv->display.funcs.dpll = &mtl_dpll_funcs; - else if (IS_DG2(dev_priv)) - dev_priv->display.funcs.dpll = &dg2_dpll_funcs; - else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv)) - dev_priv->display.funcs.dpll = &hsw_dpll_funcs; +intel_dpll_init_clock_hook(struct intel_display *display) +{ + struct drm_i915_private *dev_priv = to_i915(display->drm); + + if (DISPLAY_VER(display) >= 14) + display->funcs.dpll = &mtl_dpll_funcs; + else if (display->platform.dg2) + display->funcs.dpll = &dg2_dpll_funcs; + else if (DISPLAY_VER(display) >= 9 || HAS_DDI(display)) + display->funcs.dpll = &hsw_dpll_funcs; else if (HAS_PCH_SPLIT(dev_priv)) - dev_priv->display.funcs.dpll = &ilk_dpll_funcs; - else if (IS_CHERRYVIEW(dev_priv)) - dev_priv->display.funcs.dpll = &chv_dpll_funcs; - else if (IS_VALLEYVIEW(dev_priv)) - dev_priv->display.funcs.dpll = &vlv_dpll_funcs; - else if (IS_G4X(dev_priv)) - dev_priv->display.funcs.dpll = &g4x_dpll_funcs; - else if (IS_PINEVIEW(dev_priv)) - dev_priv->display.funcs.dpll = &pnv_dpll_funcs; - else if (DISPLAY_VER(dev_priv) != 2) - dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; + display->funcs.dpll = &ilk_dpll_funcs; + else if (display->platform.cherryview) + display->funcs.dpll = &chv_dpll_funcs; + else if (display->platform.valleyview) + display->funcs.dpll = &vlv_dpll_funcs; + else if (display->platform.g4x) + display->funcs.dpll = &g4x_dpll_funcs; + else if (display->platform.pineview) + display->funcs.dpll = &pnv_dpll_funcs; + else if (DISPLAY_VER(display) != 2) + display->funcs.dpll = &i9xx_dpll_funcs; else - dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; + display->funcs.dpll = &i8xx_dpll_funcs; } -static bool i9xx_has_pps(struct drm_i915_private *dev_priv) +static bool i9xx_has_pps(struct intel_display *display) { - if (IS_I830(dev_priv)) + if (display->platform.i830) return false; - return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); + return display->platform.pineview || display->platform.mobile; } void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; int i; @@ -1847,27 +1834,27 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) assert_transcoder_disabled(display, crtc_state->cpu_transcoder); /* PLL is protected by panel, make sure we can write it */ - if (i9xx_has_pps(dev_priv)) + if (i9xx_has_pps(display)) assert_pps_unlocked(display, pipe); - intel_de_write(dev_priv, FP0(pipe), hw_state->fp0); - intel_de_write(dev_priv, FP1(pipe), hw_state->fp1); + intel_de_write(display, FP0(pipe), hw_state->fp0); + intel_de_write(display, FP1(pipe), hw_state->fp1); /* * Apparently we need to have VGA mode enabled prior to changing * the P1/P2 dividers. Otherwise the DPLL will keep using the old * dividers, even though the register value does change. */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), + intel_de_write(display, DPLL(display, pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS); - intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); + intel_de_write(display, DPLL(display, pipe), hw_state->dpll); /* Wait for the clocks to stabilize. */ - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_posting_read(display, DPLL(display, pipe)); udelay(150); - if (DISPLAY_VER(dev_priv) >= 4) { - intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), + if (DISPLAY_VER(display) >= 4) { + intel_de_write(display, DPLL_MD(display, pipe), hw_state->dpll_md); } else { /* The pixel multiplier can only be updated once the @@ -1875,20 +1862,21 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) * * So write it again. */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); + intel_de_write(display, DPLL(display, pipe), hw_state->dpll); } /* We do this three times for luck */ for (i = 0; i < 3; i++) { - intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_write(display, DPLL(display, pipe), hw_state->dpll); + intel_de_posting_read(display, DPLL(display, pipe)); udelay(150); /* wait for warmup */ } } -static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, +static void vlv_pllb_recal_opamp(struct intel_display *display, enum dpio_phy phy, enum dpio_channel ch) { + struct drm_i915_private *dev_priv = to_i915(display->drm); u32 tmp; /* @@ -1917,6 +1905,7 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; @@ -1931,7 +1920,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) /* PLL B needs special handling */ if (pipe == PIPE_B) - vlv_pllb_recal_opamp(dev_priv, phy, ch); + vlv_pllb_recal_opamp(display, phy, ch); /* Set up Tx target for periodic Rcomp update */ vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f); @@ -2004,24 +1993,23 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; - intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_write(display, DPLL(display, pipe), hw_state->dpll); + intel_de_posting_read(display, DPLL(display, pipe)); udelay(150); - if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) - drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); + if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1)) + drm_err(display->drm, "DPLL %d failed to lock\n", pipe); } void vlv_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; @@ -2031,7 +2019,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) assert_pps_unlocked(display, pipe); /* Enable Refclk */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), + intel_de_write(display, DPLL(display, pipe), hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); if (hw_state->dpll & DPLL_VCO_ENABLE) { @@ -2039,8 +2027,8 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) _vlv_enable_pll(crtc_state); } - intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md); - intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe)); + intel_de_write(display, DPLL_MD(display, pipe), hw_state->dpll_md); + intel_de_posting_read(display, DPLL_MD(display, pipe)); } static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) @@ -2134,6 +2122,7 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; @@ -2157,18 +2146,17 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) udelay(1); /* Enable PLL */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); + intel_de_write(display, DPLL(display, pipe), hw_state->dpll); /* Check PLL is locked */ - if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) - drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); + if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1)) + drm_err(display->drm, "PLL %d failed to lock\n", pipe); } void chv_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; @@ -2178,7 +2166,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) assert_pps_unlocked(display, pipe); /* Enable Refclk and SSC */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), + intel_de_write(display, DPLL(display, pipe), hw_state->dpll & ~DPLL_VCO_ENABLE); if (hw_state->dpll & DPLL_VCO_ENABLE) { @@ -2193,29 +2181,29 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) * DPLLCMD is AWOL. Use chicken bits to propagate * the value from DPLLBMD to either pipe B or C. */ - intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); - intel_de_write(dev_priv, DPLL_MD(dev_priv, PIPE_B), + intel_de_write(display, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); + intel_de_write(display, DPLL_MD(display, PIPE_B), hw_state->dpll_md); - intel_de_write(dev_priv, CBR4_VLV, 0); - dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md; + intel_de_write(display, CBR4_VLV, 0); + display->state.chv_dpll_md[pipe] = hw_state->dpll_md; /* * DPLLB VGA mode also seems to cause problems. * We should always have it disabled. */ - drm_WARN_ON(&dev_priv->drm, - (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & + drm_WARN_ON(display->drm, + (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); } else { - intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), + intel_de_write(display, DPLL_MD(display, pipe), hw_state->dpll_md); - intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe)); + intel_de_posting_read(display, DPLL_MD(display, pipe)); } } /** * vlv_force_pll_on - forcibly enable just the PLL - * @dev_priv: i915 private structure + * @display: display device * @pipe: pipe PLL to enable * @dpll: PLL configuration * @@ -2223,10 +2211,9 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) * in cases where we need the PLL enabled even when @pipe is not going to * be enabled. */ -int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, +int vlv_force_pll_on(struct intel_display *display, enum pipe pipe, const struct dpll *dpll) { - struct intel_display *display = &dev_priv->display; struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); struct intel_crtc_state *crtc_state; @@ -2239,7 +2226,7 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, crtc_state->dpll = *dpll; crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); - if (IS_CHERRYVIEW(dev_priv)) { + if (display->platform.cherryview) { chv_compute_dpll(crtc_state); chv_enable_pll(crtc_state); } else { @@ -2252,9 +2239,8 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, return 0; } -void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) +void vlv_disable_pll(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &dev_priv->display; u32 val; /* Make sure the pipe isn't still relying on us */ @@ -2269,9 +2255,9 @@ void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) intel_de_posting_read(display, DPLL(display, pipe)); } -void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) +void chv_disable_pll(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); enum dpio_channel ch = vlv_pipe_to_channel(pipe); enum dpio_phy phy = vlv_pipe_to_phy(pipe); u32 val; @@ -2317,18 +2303,18 @@ void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) /** * vlv_force_pll_off - forcibly disable just the PLL - * @dev_priv: i915 private structure + * @display: display device * @pipe: pipe PLL to disable * * Disable the PLL for @pipe. To be used in cases where we need * the PLL enabled even when @pipe is not going to be enabled. */ -void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) +void vlv_force_pll_off(struct intel_display *display, enum pipe pipe) { - if (IS_CHERRYVIEW(dev_priv)) - chv_disable_pll(dev_priv, pipe); + if (display->platform.cherryview) + chv_disable_pll(display, pipe); else - vlv_disable_pll(dev_priv, pipe); + vlv_disable_pll(display, pipe); } /* Only for pre-ILK configs */ diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h index 21d06cbd2ce7..280e90a57c87 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.h +++ b/drivers/gpu/drm/i915/display/intel_dpll.h @@ -8,16 +8,15 @@ #include +enum pipe; struct dpll; -struct drm_i915_private; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_display; struct intel_dpll_hw_state; -enum pipe; -void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv); +void intel_dpll_init_clock_hook(struct intel_display *display); int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc); int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, @@ -29,14 +28,14 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc, void vlv_compute_dpll(struct intel_crtc_state *crtc_state); void chv_compute_dpll(struct intel_crtc_state *crtc_state); -int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, +int vlv_force_pll_on(struct intel_display *display, enum pipe pipe, const struct dpll *dpll); -void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); +void vlv_force_pll_off(struct intel_display *display, enum pipe pipe); void chv_enable_pll(const struct intel_crtc_state *crtc_state); -void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe); +void chv_disable_pll(struct intel_display *display, enum pipe pipe); void vlv_enable_pll(const struct intel_crtc_state *crtc_state); -void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe); +void vlv_disable_pll(struct intel_display *display, enum pipe pipe); void i9xx_enable_pll(const struct intel_crtc_state *crtc_state); void i9xx_disable_pll(const struct intel_crtc_state *crtc_state); bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index b9b3b2803e85..4d4e2b9f5f2d 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -91,7 +91,6 @@ static void vlv_power_sequencer_kick(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum pipe pipe = intel_dp->pps.vlv_pps_pipe; bool pll_enabled, release_cl_override = false; @@ -134,7 +133,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) release_cl_override = display->platform.cherryview && !chv_phy_powergate_ch(display, phy, ch, true); - if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(display))) { + if (vlv_force_pll_on(display, pipe, vlv_get_dpll(display))) { drm_err(display->drm, "Failed to force on PLL for pipe %c!\n", pipe_name(pipe)); @@ -158,7 +157,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) intel_de_posting_read(display, intel_dp->output_reg); if (!pll_enabled) { - vlv_force_pll_off(dev_priv, pipe); + vlv_force_pll_off(display, pipe); if (release_cl_override) chv_phy_powergate_ch(display, phy, ch, false); -- 2.51.0 From fe11acc33154528027033051f02be133b356032f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 25 Mar 2025 14:36:34 +0200 Subject: [PATCH 16/16] drm/i915/ddi: convert intel_ddi.c to struct intel_display MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Going forward, struct intel_display is the main display device data pointer. Convert as much as possible of intel_ddi.c to struct intel_display. Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/44aebcf93b2211e917b2ee725433b1f9b5e4e6f6.1742906146.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 904 +++++++++++------------ 1 file changed, 437 insertions(+), 467 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 44f4465c27e2..56068b2ef964 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -107,14 +107,14 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder, return level; } -static bool has_buf_trans_select(struct drm_i915_private *i915) +static bool has_buf_trans_select(struct intel_display *display) { - return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); + return DISPLAY_VER(display) < 10 && !display->platform.broxton; } -static bool has_iboost(struct drm_i915_private *i915) +static bool has_iboost(struct intel_display *display) { - return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); + return DISPLAY_VER(display) == 9 && !display->platform.broxton; } /* @@ -125,25 +125,25 @@ static bool has_iboost(struct drm_i915_private *i915) void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); u32 iboost_bit = 0; int i, n_entries; enum port port = encoder->port; const struct intel_ddi_buf_trans *trans; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; /* If we're boosting the current, set bit 31 of trans1 */ - if (has_iboost(dev_priv) && + if (has_iboost(display) && intel_bios_dp_boost_level(encoder->devdata)) iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; for (i = 0; i < n_entries; i++) { - intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), + intel_de_write(display, DDI_BUF_TRANS_LO(port, i), trans->entries[i].hsw.trans1 | iboost_bit); - intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), + intel_de_write(display, DDI_BUF_TRANS_HI(port, i), trans->entries[i].hsw.trans2); } } @@ -156,7 +156,7 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); int level = intel_ddi_level(encoder, crtc_state, 0); u32 iboost_bit = 0; int n_entries; @@ -164,27 +164,25 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, const struct intel_ddi_buf_trans *trans; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; /* If we're boosting the current, set bit 31 of trans1 */ - if (has_iboost(dev_priv) && + if (has_iboost(display) && intel_bios_hdmi_boost_level(encoder->devdata)) iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; /* Entry 9 is for HDMI: */ - intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), + intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), trans->entries[level].hsw.trans1 | iboost_bit); - intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), + intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), trans->entries[level].hsw.trans2); } static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (DISPLAY_VER(display) >= 14) - return XELPDP_PORT_BUF_CTL1(i915, port); + return XELPDP_PORT_BUF_CTL1(display, port); else return DDI_BUF_CTL(port); } @@ -347,7 +345,6 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -360,14 +357,14 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, if (dig_port->ddi_a_4_lanes) intel_dp->DP |= DDI_A_4_LANES; - if (DISPLAY_VER(i915) >= 14) { + if (DISPLAY_VER(display) >= 14) { if (intel_dp_is_uhbr(crtc_state)) intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; else intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; } - if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { + if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); if (!intel_tc_port_in_tbt_alt_mode(dig_port)) intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; @@ -380,8 +377,7 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, } } -static int icl_calc_tbt_pll_link(struct intel_display *display, - enum port port) +static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) { u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; @@ -415,15 +411,14 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 temp; if (!intel_crtc_has_dp_encoder(crtc_state)) return; - drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); + drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); temp = DP_MSA_MISC_SYNC_CLOCK; @@ -446,7 +441,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, } /* nonsense combination */ - drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && + drm_WARN_ON(display->drm, crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); if (crtc_state->limited_color_range) @@ -469,7 +464,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) temp |= DP_MSA_MISC_COLOR_VSC_SDP; - intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), temp); } @@ -508,8 +503,8 @@ static u32 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum port port = encoder->port; @@ -517,7 +512,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ temp = TRANS_DDI_FUNC_ENABLE; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) temp |= TGL_TRANS_DDI_SELECT_PORT(port); else temp |= TRANS_DDI_SELECT_PORT(port); @@ -579,7 +574,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, temp |= TRANS_DDI_HDMI_SCRAMBLING; if (crtc_state->hdmi_high_tmds_clock_ratio) temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER(display) >= 14) temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; @@ -592,11 +587,11 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, temp |= TRANS_DDI_MODE_SELECT_DP_MST; temp |= DDI_PORT_WIDTH(crtc_state->lane_count); - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(display) >= 12) { enum transcoder master; master = crtc_state->mst_master_transcoder; - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(display->drm, master == INVALID_TRANSCODER); temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); } @@ -605,7 +600,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, temp |= DDI_PORT_WIDTH(crtc_state->lane_count); } - if (IS_DISPLAY_VER(dev_priv, 8, 10) && + if (IS_DISPLAY_VER(display, 8, 10) && crtc_state->master_transcoder != INVALID_TRANSCODER) { u8 master_select = bdw_trans_port_sync_master_select(crtc_state->master_transcoder); @@ -620,11 +615,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (DISPLAY_VER(dev_priv) >= 11) { + if (DISPLAY_VER(display) >= 11) { enum transcoder master_transcoder = crtc_state->master_transcoder; u32 ctl2 = 0; @@ -636,12 +630,12 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, PORT_SYNC_MODE_MASTER_SELECT(master_select); } - intel_de_write(dev_priv, - TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), + intel_de_write(display, + TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), ctl2); } - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state)); } @@ -655,8 +649,7 @@ void intel_ddi_config_transcoder_func(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 ctl; @@ -664,7 +657,7 @@ intel_ddi_config_transcoder_func(struct intel_encoder *encoder, ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); ctl &= ~TRANS_DDI_FUNC_ENABLE; - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), ctl); } @@ -678,27 +671,26 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 ctl; - if (DISPLAY_VER(dev_priv) >= 11) - intel_de_write(dev_priv, - TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), + if (DISPLAY_VER(display) >= 11) + intel_de_write(display, + TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0); - ctl = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); + ctl = intel_de_read(display, + TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); ctl &= ~TRANS_DDI_FUNC_ENABLE; - if (IS_DISPLAY_VER(dev_priv, 8, 10)) + if (IS_DISPLAY_VER(display, 8, 10)) ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(display) >= 12) { if (!intel_dp_mst_is_master_trans(crtc_state)) { ctl &= ~(TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); @@ -707,7 +699,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); } - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), ctl); if (intel_dp_mst_is_slave_trans(crtc_state)) @@ -726,17 +718,15 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, bool enable, u32 hdcp_mask) { struct intel_display *display = to_intel_display(intel_encoder); - struct drm_device *dev = intel_encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); intel_wakeref_t wakeref; int ret = 0; wakeref = intel_display_power_get_if_enabled(display, intel_encoder->power_domain); - if (drm_WARN_ON(dev, !wakeref)) + if (drm_WARN_ON(display->drm, !wakeref)) return -ENXIO; - intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), hdcp_mask, enable ? hdcp_mask : 0); intel_display_power_put(display, intel_encoder->power_domain, wakeref); return ret; @@ -745,7 +735,6 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) { struct intel_display *display = to_intel_display(intel_connector); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder = intel_attached_encoder(intel_connector); int type = intel_connector->base.connector_type; enum port port = encoder->port; @@ -766,12 +755,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) goto out; } - if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) + if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) cpu_transcoder = TRANSCODER_EDP; else cpu_transcoder = (enum transcoder) pipe; - ddi_mode = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & + ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_MODE_SELECT_MASK; if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || @@ -805,7 +794,6 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, u8 *pipe_mask, bool *is_dp_mst) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum port port = encoder->port; intel_wakeref_t wakeref; enum pipe p; @@ -820,13 +808,13 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if (!wakeref) return; - tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); + tmp = intel_de_read(display, DDI_BUF_CTL(port)); if (!(tmp & DDI_BUF_CTL_ENABLE)) goto out; - if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { - tmp = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)); + if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { + tmp = intel_de_read(display, + TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { default: @@ -847,7 +835,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, goto out; } - for_each_pipe(dev_priv, p) { + for_each_pipe(display, p) { enum transcoder cpu_transcoder = (enum transcoder)p; u32 port_mask, ddi_select, ddi_mode; intel_wakeref_t trans_wakeref; @@ -857,7 +845,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if (!trans_wakeref) continue; - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(display) >= 12) { port_mask = TGL_TRANS_DDI_PORT_MASK; ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); } else { @@ -865,8 +853,8 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, ddi_select = TRANS_DDI_SELECT_PORT(port); } - tmp = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); + tmp = intel_de_read(display, + TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), trans_wakeref); @@ -884,7 +872,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, } if (!*pipe_mask) - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "No pipe for [ENCODER:%d:%s] found\n", encoder->base.base.id, encoder->base.name); @@ -907,7 +895,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, } if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", encoder->base.base.id, encoder->base.name, *pipe_mask); @@ -915,7 +903,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, } if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", encoder->base.base.id, encoder->base.name, *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); @@ -923,12 +911,12 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, *is_dp_mst = mst_pipe_mask; out: - if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { - tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); + if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { + tmp = intel_de_read(display, BXT_PHY_CTL(port)); if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | BXT_PHY_LANE_POWERDOWN_ACK | BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) - drm_err(&dev_priv->drm, + drm_err(display->drm, "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", encoder->base.base.id, encoder->base.name, tmp); } @@ -1042,8 +1030,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum phy phy = intel_encoder_to_phy(encoder); u32 val; @@ -1051,53 +1038,53 @@ void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, if (cpu_transcoder == TRANSCODER_EDP) return; - if (DISPLAY_VER(dev_priv) >= 13) + if (DISPLAY_VER(display) >= 13) val = TGL_TRANS_CLK_SEL_PORT(phy); - else if (DISPLAY_VER(dev_priv) >= 12) + else if (DISPLAY_VER(display) >= 12) val = TGL_TRANS_CLK_SEL_PORT(encoder->port); else val = TRANS_CLK_SEL_PORT(encoder->port); - intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); + intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); } void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 val; if (cpu_transcoder == TRANSCODER_EDP) return; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) val = TGL_TRANS_CLK_SEL_DISABLED; else val = TRANS_CLK_SEL_DISABLED; - intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); + intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); } -static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, +static void _skl_ddi_set_iboost(struct intel_display *display, enum port port, u8 iboost) { u32 tmp; - tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); + tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); if (iboost) tmp |= iboost << BALANCE_LEG_SHIFT(port); else tmp |= BALANCE_LEG_DISABLE(port); - intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); + intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); } static void skl_ddi_set_iboost(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int level) { + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u8 iboost; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) @@ -1110,7 +1097,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, int n_entries; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; iboost = trans->entries[level].hsw.i_boost; @@ -1118,28 +1105,28 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, /* Make sure that the requested I_boost is valid */ if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { - drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); + drm_err(display->drm, "Invalid I_boost value %u\n", iboost); return; } - _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); + _skl_ddi_set_iboost(display, encoder->port, iboost); if (encoder->port == PORT_A && dig_port->max_lanes == 4) - _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); + _skl_ddi_set_iboost(display, PORT_E, iboost); } static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(intel_dp); struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int n_entries; encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) + if (drm_WARN_ON(display->drm, n_entries < 1)) n_entries = 1; - if (drm_WARN_ON(&dev_priv->drm, + if (drm_WARN_ON(display->drm, n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) n_entries = ARRAY_SIZE(index_to_dp_signal_levels); @@ -1172,14 +1159,14 @@ static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_stat static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_ddi_buf_trans *trans; enum phy phy = intel_encoder_to_phy(encoder); int n_entries, ln; u32 val; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { @@ -1187,25 +1174,25 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; intel_dp->hobl_active = is_hobl_buf_trans(trans); - intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, + intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, intel_dp->hobl_active ? val : 0); } /* Set PORT_TX_DW5 */ - val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); + val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | COEFF_POLARITY | CURSOR_PROGRAM | TAP2_DISABLE | TAP3_DISABLE); val |= SCALING_MODE_SEL(0x2); val |= RTERM_SELECT(0x6); val |= TAP3_DISABLE; - intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); + intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); /* Program PORT_TX_DW2 */ for (ln = 0; ln < 4; ln++) { int level = intel_ddi_level(encoder, crtc_state, ln); - intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), + intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | @@ -1217,7 +1204,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, for (ln = 0; ln < 4; ln++) { int level = intel_ddi_level(encoder, crtc_state, ln); - intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), + intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | @@ -1228,7 +1215,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, for (ln = 0; ln < 4; ln++) { int level = intel_ddi_level(encoder, crtc_state, ln); - intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), + intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), N_SCALAR_MASK, N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); } @@ -1237,7 +1224,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); u32 val; int ln; @@ -1247,12 +1234,12 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, * set PORT_PCS_DW1 cmnkeeper_enable to 1b, * else clear to 0b. */ - val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); + val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) val &= ~COMMON_KEEPER_EN; else val |= COMMON_KEEPER_EN; - intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); + intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); /* 2. Program loadgen select */ /* @@ -1262,33 +1249,33 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) */ for (ln = 0; ln < 4; ln++) { - intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), + intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), LOADGEN_SELECT, icl_combo_phy_loadgen_select(crtc_state, ln)); } /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ - intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), + intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG); /* 4. Clear training enable to change swing values */ - val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); + val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); val &= ~TX_TRAINING_EN; - intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); + intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); /* 5. Program swing and de-emphasis */ icl_ddi_combo_vswing_program(encoder, crtc_state); /* 6. Set training enable to trigger update */ - val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); + val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); val |= TX_TRAINING_EN; - intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); + intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); } static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); const struct intel_ddi_buf_trans *trans; int n_entries, ln; @@ -1297,13 +1284,13 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, return; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; for (ln = 0; ln < 2; ln++) { - intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), + intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), CRI_USE_FS32, 0); - intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), + intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), CRI_USE_FS32, 0); } @@ -1313,13 +1300,13 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, level = intel_ddi_level(encoder, crtc_state, 2*ln+0); - intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), + intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), CRI_TXDEEMPH_OVERRIDE_17_12_MASK, CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); level = intel_ddi_level(encoder, crtc_state, 2*ln+1); - intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), + intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), CRI_TXDEEMPH_OVERRIDE_17_12_MASK, CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); } @@ -1330,7 +1317,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, level = intel_ddi_level(encoder, crtc_state, 2*ln+0); - intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), + intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK, CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | @@ -1339,7 +1326,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, level = intel_ddi_level(encoder, crtc_state, 2*ln+1); - intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), + intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK, CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | @@ -1355,21 +1342,21 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, * values from table for which TX1 and TX2 enabled. */ for (ln = 0; ln < 2; ln++) { - intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), + intel_de_rmw(display, MG_CLKHUB(ln, tc_port), CFG_LOW_RATE_LKREN_EN, crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); } /* Program the MG_TX_DCC based on the link frequency */ for (ln = 0; ln < 2; ln++) { - intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), + intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | CFG_AMI_CK_DIV_OVERRIDE_EN, crtc_state->port_clock > 500000 ? CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | CFG_AMI_CK_DIV_OVERRIDE_EN : 0); - intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), + intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | CFG_AMI_CK_DIV_OVERRIDE_EN, crtc_state->port_clock > 500000 ? @@ -1379,9 +1366,9 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, /* Program MG_TX_PISO_READLOAD with values from vswing table */ for (ln = 0; ln < 2; ln++) { - intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), + intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 0, CRI_CALCINIT); - intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), + intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 0, CRI_CALCINIT); } } @@ -1491,12 +1478,12 @@ int intel_ddi_level(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int lane) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_ddi_buf_trans *trans; int level, n_entries; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&i915->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return 0; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) @@ -1505,7 +1492,7 @@ int intel_ddi_level(struct intel_encoder *encoder, level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, lane); - if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) + if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) level = n_entries - 1; return level; @@ -1515,13 +1502,13 @@ static void hsw_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); int level = intel_ddi_level(encoder, crtc_state, 0); enum port port = encoder->port; u32 signal_levels; - if (has_iboost(dev_priv)) + if (has_iboost(display)) skl_ddi_set_iboost(encoder, crtc_state, level); /* HDMI ignores the rest */ @@ -1530,46 +1517,46 @@ hsw_set_signal_levels(struct intel_encoder *encoder, signal_levels = DDI_BUF_TRANS_SELECT(level); - drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", + drm_dbg_kms(display->drm, "Using signal levels %08x\n", signal_levels); intel_dp->DP &= ~DDI_BUF_EMP_MASK; intel_dp->DP |= signal_levels; - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); - intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); + intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); + intel_de_posting_read(display, DDI_BUF_CTL(port)); } -static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, +static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, u32 clk_sel_mask, u32 clk_sel, u32 clk_off) { - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); + intel_de_rmw(display, reg, clk_sel_mask, clk_sel); /* * "This step and the step before must be * done with separate register writes." */ - intel_de_rmw(i915, reg, clk_off, 0); + intel_de_rmw(display, reg, clk_off, 0); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } -static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, +static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, u32 clk_off) { - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, reg, 0, clk_off); + intel_de_rmw(display, reg, 0, clk_off); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } -static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, +static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, u32 clk_off) { - return !(intel_de_read(i915, reg) & clk_off); + return !(intel_de_read(display, reg) & clk_off); } static struct intel_shared_dpll * @@ -1586,14 +1573,14 @@ _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, static void adls_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_encoder_to_phy(encoder); - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), + _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); @@ -1601,19 +1588,19 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder, static void adls_ddi_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), + _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), + return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } @@ -1630,14 +1617,14 @@ static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) static void rkl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_encoder_to_phy(encoder); - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, + _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); @@ -1645,19 +1632,19 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder, static void rkl_ddi_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, + _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, + return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } @@ -1674,23 +1661,23 @@ static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) static void dg1_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_encoder_to_phy(encoder); - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; /* * If we fail this, something went very wrong: first 2 PLLs should be * used by first 2 phys and last 2 PLLs by last phys */ - if (drm_WARN_ON(&i915->drm, + if (drm_WARN_ON(display->drm, (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) return; - _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), + _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); @@ -1698,19 +1685,19 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, static void dg1_ddi_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), + _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), + return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } @@ -1740,14 +1727,14 @@ static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_encoder_to_phy(encoder); - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, + _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); @@ -1755,19 +1742,19 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, + _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, + return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } @@ -1784,39 +1771,39 @@ struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; /* * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. * MG does not exist, but the programming is required to ungate DDIC and DDID." */ - intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); + intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); icl_ddi_combo_enable_clock(encoder, crtc_state); } static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; icl_ddi_combo_disable_clock(encoder); - intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); + intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); } static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; u32 tmp; - tmp = intel_de_read(i915, DDI_CLK_SEL(port)); + tmp = intel_de_read(display, DDI_CLK_SEL(port)); if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) return false; @@ -1827,54 +1814,54 @@ static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum tc_port tc_port = intel_encoder_to_tc(encoder); enum port port = encoder->port; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - intel_de_write(i915, DDI_CLK_SEL(port), + intel_de_write(display, DDI_CLK_SEL(port), icl_pll_to_ddi_clk_sel(encoder, crtc_state)); - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, + intel_de_rmw(display, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); enum port port = encoder->port; - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, + intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); - intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); + intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); } static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); enum port port = encoder->port; u32 tmp; - tmp = intel_de_read(i915, DDI_CLK_SEL(port)); + tmp = intel_de_read(display, DDI_CLK_SEL(port)); if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) return false; - tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); + tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); } @@ -1935,47 +1922,47 @@ static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) static void skl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, DPLL_CTRL2, + intel_de_rmw(display, DPLL_CTRL2, DPLL_CTRL2_DDI_CLK_OFF(port) | DPLL_CTRL2_DDI_CLK_SEL_MASK(port), DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } static void skl_ddi_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, DPLL_CTRL2, + intel_de_rmw(display, DPLL_CTRL2, 0, DPLL_CTRL2_DDI_CLK_OFF(port)); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; /* * FIXME Not sure if the override affects both * the PLL selection and the CLK_OFF bit. */ - return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); + return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); } static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) @@ -2003,30 +1990,30 @@ static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) void hsw_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); + intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); } void hsw_ddi_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); + intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); } bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; + return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; } static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) @@ -2082,7 +2069,7 @@ void intel_ddi_disable_clock(struct intel_encoder *encoder) void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); u32 port_mask; bool ddi_clk_needed; @@ -2102,7 +2089,7 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) * In the unlikely case that BIOS enables DP in MST mode, just * warn since our MST HW readout is incomplete. */ - if (drm_WARN_ON(&i915->drm, is_mst)) + if (drm_WARN_ON(display->drm, is_mst)) return; } @@ -2117,11 +2104,11 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) * Sanity check that we haven't incorrectly registered another * encoder using any of the ports of this DSI encoder. */ - for_each_intel_encoder(&i915->drm, other_encoder) { + for_each_intel_encoder(display->drm, other_encoder) { if (other_encoder == encoder) continue; - if (drm_WARN_ON(&i915->drm, + if (drm_WARN_ON(display->drm, port_mask & BIT(other_encoder->port))) return; } @@ -2136,7 +2123,7 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) !encoder->is_clock_enabled(encoder)) return; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", encoder->base.base.id, encoder->base.name); @@ -2256,10 +2243,10 @@ tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - if (DISPLAY_VER(dev_priv) >= 12) - return TGL_DP_TP_CTL(dev_priv, + if (DISPLAY_VER(display) >= 12) + return TGL_DP_TP_CTL(display, tgl_dp_tp_transcoder(crtc_state)); else return DP_TP_CTL(encoder->port); @@ -2268,10 +2255,10 @@ i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - if (DISPLAY_VER(dev_priv) >= 12) - return TGL_DP_TP_STATUS(dev_priv, + if (DISPLAY_VER(display) >= 12) + return TGL_DP_TP_STATUS(display, tgl_dp_tp_transcoder(crtc_state)); else return DP_TP_STATUS(encoder->port); @@ -2446,14 +2433,14 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder, static void intel_ddi_disable_fec(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); if (!crtc_state->fec_enable) return; - intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), + intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), DP_TP_CTL_FEC_ENABLE, 0); - intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); + intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); } static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, @@ -2475,11 +2462,11 @@ static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, * Splitter enable for eDP MSO is limited to certain pipes, on certain * platforms. */ -static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) +static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) { - if (DISPLAY_VER(i915) > 20) + if (DISPLAY_VER(display) > 20) return ~0; - else if (IS_ALDERLAKE_P(i915)) + else if (display->platform.alderlake_p) return BIT(PIPE_A) | BIT(PIPE_B); else return BIT(PIPE_A); @@ -2488,28 +2475,28 @@ static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) static void intel_ddi_mso_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { + struct intel_display *display = to_intel_display(pipe_config); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 dss1; - if (!HAS_MSO(i915)) + if (!HAS_MSO(display)) return; - dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); + dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; if (!pipe_config->splitter.enable) return; - if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { + if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { pipe_config->splitter.enable = false; return; } switch (dss1 & SPLITTER_CONFIGURATION_MASK) { default: - drm_WARN(&i915->drm, true, + drm_WARN(display->drm, true, "Invalid splitter configuration, dss1=0x%08x\n", dss1); fallthrough; case SPLITTER_CONFIGURATION_2_SEGMENT: @@ -2525,12 +2512,12 @@ static void intel_ddi_mso_get_config(struct intel_encoder *encoder, static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 dss1 = 0; - if (!HAS_MSO(i915)) + if (!HAS_MSO(display)) return; if (crtc_state->splitter.enable) { @@ -2542,7 +2529,7 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; } - intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), + intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | OVERLAP_PIXELS_MASK, dss1); } @@ -2550,27 +2537,27 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) static void mtl_ddi_enable_d2d(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; i915_reg_t reg; u32 set_bits, wait_bits; - if (DISPLAY_VER(dev_priv) < 14) + if (DISPLAY_VER(display) < 14) return; - if (DISPLAY_VER(dev_priv) >= 20) { + if (DISPLAY_VER(display) >= 20) { reg = DDI_BUF_CTL(port); set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; } else { - reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); + reg = XELPDP_PORT_BUF_CTL1(display, port); set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; } - intel_de_rmw(dev_priv, reg, 0, set_bits); - if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { - drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", + intel_de_rmw(display, reg, 0, set_bits); + if (wait_for_us(intel_de_read(display, reg) & wait_bits, 100)) { + drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", port_name(port)); } } @@ -2600,13 +2587,13 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); u32 val; val = intel_tc_port_in_tbt_alt_mode(dig_port) ? XELPDP_PORT_BUF_IO_SELECT_TBT : 0; - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), + intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), XELPDP_PORT_BUF_IO_SELECT_TBT, val); } @@ -2735,7 +2722,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); int ret; @@ -2779,7 +2765,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { - drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); + drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); } @@ -2883,16 +2869,15 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); - if (DISPLAY_VER(dev_priv) < 11) - drm_WARN_ON(&dev_priv->drm, + if (DISPLAY_VER(display) < 11) + drm_WARN_ON(display->drm, is_mst && (port == PORT_A || port == PORT_E)); else - drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); + drm_WARN_ON(display->drm, is_mst && port == PORT_A); intel_dp_set_link_params(intel_dp, crtc_state->port_clock, @@ -2909,14 +2894,14 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, intel_ddi_enable_clock(encoder, crtc_state); if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { - drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); + drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); } icl_program_mg_dp_mode(dig_port, crtc_state); - if (has_buf_trans_select(dev_priv)) + if (has_buf_trans_select(display)) hsw_prepare_dp_ddi_buffers(encoder, crtc_state); encoder->set_signal_levels(encoder, crtc_state); @@ -2932,7 +2917,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, crtc_state); intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); intel_dp_start_link_train(state, intel_dp, crtc_state); - if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && + if ((port != PORT_A || DISPLAY_VER(display) >= 9) && !is_trans_port_sync_mode(crtc_state)) intel_dp_stop_link_train(intel_dp, crtc_state); @@ -2980,12 +2965,11 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); intel_ddi_enable_clock(encoder, crtc_state); - drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); + drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); @@ -3023,10 +3007,9 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); + drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); intel_set_cpu_fifo_underrun_reporting(display, pipe, true); @@ -3051,27 +3034,27 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, static void mtl_ddi_disable_d2d(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; i915_reg_t reg; u32 clr_bits, wait_bits; - if (DISPLAY_VER(dev_priv) < 14) + if (DISPLAY_VER(display) < 14) return; - if (DISPLAY_VER(dev_priv) >= 20) { + if (DISPLAY_VER(display) >= 20) { reg = DDI_BUF_CTL(port); clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; } else { - reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); + reg = XELPDP_PORT_BUF_CTL1(display, port); clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; } - intel_de_rmw(dev_priv, reg, clr_bits, 0); - if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) - drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", + intel_de_rmw(display, reg, clr_bits, 0); + if (wait_for_us(!(intel_de_read(display, reg) & wait_bits), 100)) + drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", port_name(port)); } @@ -3090,10 +3073,9 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); + intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); if (DISPLAY_VER(display) >= 14) intel_wait_ddi_buf_idle(display, port); @@ -3101,7 +3083,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder, mtl_ddi_disable_d2d(encoder); if (intel_crtc_has_dp_encoder(crtc_state)) { - intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), + intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), DP_TP_CTL_ENABLE, 0); } @@ -3119,7 +3101,6 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = &dig_port->dp; intel_wakeref_t wakeref; @@ -3136,12 +3117,12 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, */ intel_dp_set_power(intel_dp, DP_SET_POWER_D3); - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(display) >= 12) { if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; - intel_de_rmw(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + intel_de_rmw(display, + TRANS_DDI_FUNC_CTL(display, cpu_transcoder), TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 0); } @@ -3161,7 +3142,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, * Configure Transcoder Clock select to direct no clock to the * transcoder" */ - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) intel_ddi_disable_transcoder_clock(old_crtc_state); intel_pps_vdd_on(intel_dp); @@ -3177,8 +3158,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, intel_ddi_disable_clock(encoder); /* De-select Thunderbolt */ - if (DISPLAY_VER(dev_priv) >= 14) - intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), + if (DISPLAY_VER(display) >= 14) + intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), XELPDP_PORT_BUF_IO_SELECT_TBT, 0); } @@ -3188,7 +3169,6 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; intel_wakeref_t wakeref; @@ -3196,12 +3176,12 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, dig_port->set_infoframes(encoder, false, old_crtc_state, old_conn_state); - if (DISPLAY_VER(dev_priv) < 12) + if (DISPLAY_VER(display) < 12) intel_ddi_disable_transcoder_clock(old_crtc_state); intel_ddi_buf_disable(encoder, old_crtc_state); - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) intel_ddi_disable_transcoder_clock(old_crtc_state); wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); @@ -3221,7 +3201,6 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_crtc *pipe_crtc; bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); @@ -3260,7 +3239,7 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, intel_dsc_disable(old_pipe_crtc_state); - if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(display) >= 9) skl_scaler_disable(old_pipe_crtc_state); else ilk_pfit_disable(old_pipe_crtc_state); @@ -3362,12 +3341,12 @@ static void intel_ddi_enable_dp(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); enum port port = encoder->port; - if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) + if (port == PORT_A && DISPLAY_VER(display) < 9) intel_dp_stop_link_train(intel_dp, crtc_state); drm_connector_update_privacy_screen(conn_state); @@ -3404,7 +3383,6 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_connector *connector = conn_state->connector; enum port port = encoder->port; @@ -3413,11 +3391,11 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, if (!intel_hdmi_handle_sink_scrambling(encoder, connector, crtc_state->hdmi_high_tmds_clock_ratio, crtc_state->hdmi_scrambling)) - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", connector->base.id, connector->name); - if (has_buf_trans_select(dev_priv)) + if (has_buf_trans_select(display)) hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); /* e. Enable D2D Link for C10/C20 Phy */ @@ -3426,7 +3404,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, encoder->set_signal_levels(encoder, crtc_state); /* Display WA #1143: skl,kbl,cfl */ - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { + if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { /* * For some reason these chicken bits have been * stuffed into a transcoder register, event though @@ -3436,7 +3414,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); u32 val; - val = intel_de_read(dev_priv, reg); + val = intel_de_read(display, reg); if (port == PORT_E) val |= DDIE_TRAINING_OVERRIDE_ENABLE | @@ -3445,8 +3423,8 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, val |= DDI_TRAINING_OVERRIDE_ENABLE | DDI_TRAINING_OVERRIDE_VALUE; - intel_de_write(dev_priv, reg, val); - intel_de_posting_read(dev_priv, reg); + intel_de_write(display, reg, val); + intel_de_posting_read(display, reg); udelay(1); @@ -3457,7 +3435,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | DDI_TRAINING_OVERRIDE_VALUE); - intel_de_write(dev_priv, reg, val); + intel_de_write(display, reg, val); } intel_ddi_power_up_lanes(encoder, crtc_state); @@ -3478,7 +3456,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, if (dig_port->ddi_a_4_lanes) buf_ctl |= DDI_A_4_LANES; - if (DISPLAY_VER(dev_priv) >= 14) { + if (DISPLAY_VER(display) >= 14) { u32 port_buf = 0; port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); @@ -3486,15 +3464,15 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, if (dig_port->lane_reversal) port_buf |= XELPDP_PORT_REVERSAL; - intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), + intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); - if (DISPLAY_VER(dev_priv) >= 20) + if (DISPLAY_VER(display) >= 20) buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; - } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { - drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); + } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { + drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } @@ -3589,12 +3567,12 @@ static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct drm_connector *connector = old_conn_state->connector; if (!intel_hdmi_handle_sink_scrambling(encoder, connector, false, false)) - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", connector->base.id, connector->name); } @@ -3658,16 +3636,16 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state, struct intel_encoder *encoder, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_crtc *pipe_crtc; /* FIXME: Add MTL pll_mgr */ - if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) + if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) return; - for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, + for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, intel_crtc_joined_pipe_mask(crtc_state)) intel_update_active_dpll(state, pipe_crtc, encoder); } @@ -3683,7 +3661,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_tc_port = intel_encoder_is_tc(encoder); @@ -3702,7 +3680,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, * Type-C ports. Skip this step for TBT. */ intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + else if (display->platform.geminilake || display->platform.broxton) bxt_dpio_phy_set_lane_optim_mask(encoder, crtc_state->lane_lat_optim_mask); } @@ -3770,10 +3748,9 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 dp_tp_ctl; - dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); + dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); @@ -3786,10 +3763,10 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, if (crtc_state->enhanced_framing) dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; } - intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); - intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); + intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); + intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); - if (IS_ALDERLAKE_P(dev_priv) && + if (display->platform.alderlake_p && (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) adlp_tbt_to_dp_alt_switch_wa(encoder); @@ -3801,11 +3778,11 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, u8 dp_train_pat) { + struct intel_display *display = to_intel_display(intel_dp); struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 temp; - temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); + temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; switch (intel_dp_training_pattern_symbol(dp_train_pat)) { @@ -3826,17 +3803,17 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp, break; } - intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); + intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); } static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(intel_dp); struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), + intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); /* @@ -3846,28 +3823,26 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, * In this case there is requirement to wait for a minimum number of * idle patterns to be sent. */ - if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) + if (port == PORT_A && DISPLAY_VER(display) < 12) return; - if (intel_de_wait_for_set(dev_priv, + if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), DP_TP_STATUS_IDLE_DONE, 2)) - drm_err(&dev_priv->drm, + drm_err(display->drm, "Timed out waiting for DP idle patterns\n"); } -static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, +static bool intel_ddi_is_audio_enabled(struct intel_display *display, enum transcoder cpu_transcoder) { - struct intel_display *display = &dev_priv->display; - if (cpu_transcoder == TRANSCODER_EDP) return false; if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) return false; - return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & + return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & AUDIO_OUTPUT_ENABLE(cpu_transcoder); } @@ -3897,34 +3872,34 @@ static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER(display) >= 14) crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); - else if (DISPLAY_VER(dev_priv) >= 12) + else if (DISPLAY_VER(display) >= 12) crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); - else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) + else if (display->platform.jasperlake || display->platform.elkhartlake) crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); - else if (DISPLAY_VER(dev_priv) >= 11) + else if (DISPLAY_VER(display) >= 11) crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); } -static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, +static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, enum transcoder cpu_transcoder) { u32 master_select; - if (DISPLAY_VER(dev_priv) >= 11) { - u32 ctl2 = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder)); + if (DISPLAY_VER(display) >= 11) { + u32 ctl2 = intel_de_read(display, + TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) return INVALID_TRANSCODER; master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); } else { - u32 ctl = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); + u32 ctl = intel_de_read(display, + TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) return INVALID_TRANSCODER; @@ -3941,15 +3916,14 @@ static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *de static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D); enum transcoder cpu_transcoder; crtc_state->master_transcoder = - bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); + bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); - for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { + for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { enum intel_display_power_domain power_domain; intel_wakeref_t trans_wakeref; @@ -3960,14 +3934,14 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) if (!trans_wakeref) continue; - if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == + if (bdw_transcoder_master_readout(display, cpu_transcoder) == crtc_state->cpu_transcoder) crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); intel_display_power_put(display, power_domain, trans_wakeref); } - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(display->drm, crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask); } @@ -4090,11 +4064,10 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; u32 ddi_func_ctl, ddi_mode, flags = 0; - ddi_func_ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); + ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); if (ddi_func_ctl & TRANS_DDI_PHSYNC) flags |= DRM_MODE_FLAG_PHSYNC; else @@ -4157,11 +4130,11 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, static void intel_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; /* XXX: DSI transcoder paranoia */ - if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) + if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) return; intel_ddi_read_func_ctl(encoder, pipe_config); @@ -4169,14 +4142,14 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, intel_ddi_mso_get_config(encoder, pipe_config); pipe_config->has_audio = - intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); + intel_ddi_is_audio_enabled(display, cpu_transcoder); if (encoder->type == INTEL_OUTPUT_EDP) intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); ddi_dotclock_get(pipe_config); - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (display->platform.geminilake || display->platform.broxton) pipe_config->lane_lat_optim_mask = bxt_dpio_phy_get_lane_lat_optim_mask(encoder); @@ -4197,7 +4170,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, HDMI_INFOFRAME_TYPE_DRM, &pipe_config->infoframes.drm); - if (DISPLAY_VER(dev_priv) >= 8) + if (DISPLAY_VER(display) >= 8) bdw_get_trans_port_sync_config(pipe_config); intel_psr_get_config(encoder, pipe_config); @@ -4290,10 +4263,10 @@ static enum icl_port_dpll_id icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return ICL_PORT_DPLL_DEFAULT; if (icl_ddi_tc_pll_is_tbt(pll)) @@ -4387,11 +4360,11 @@ static void intel_ddi_sync_state(struct intel_encoder *encoder, static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); bool fastset = true; if (intel_encoder_is_tc(encoder)) { - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", encoder->base.base.id, encoder->base.name); crtc_state->uapi.mode_changed = true; fastset = false; @@ -4426,12 +4399,12 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; int ret; - if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) + if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) pipe_config->cpu_transcoder = TRANSCODER_EDP; if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { @@ -4446,13 +4419,13 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, if (ret) return ret; - if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && + if (display->platform.haswell && crtc->pipe == PIPE_A && pipe_config->cpu_transcoder == TRANSCODER_EDP) pipe_config->pch_pfit.force_thru = pipe_config->pch_pfit.enabled || pipe_config->crc_enabled; - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (display->platform.geminilake || display->platform.broxton) pipe_config->lane_lat_optim_mask = bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); @@ -4503,9 +4476,9 @@ static u8 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, int tile_group_id) { + struct intel_display *display = to_intel_display(ref_crtc_state); struct drm_connector *connector; const struct drm_connector_state *conn_state; - struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); struct intel_atomic_state *state = to_intel_atomic_state(ref_crtc_state->uapi.state); u8 transcoders = 0; @@ -4515,7 +4488,7 @@ intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, * We don't enable port sync on BDW due to missing w/as and * due to not having adjusted the modeset sequence appropriately. */ - if (DISPLAY_VER(dev_priv) < 9) + if (DISPLAY_VER(display) < 9) return 0; if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) @@ -4547,11 +4520,11 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct drm_connector *connector = conn_state->connector; u8 port_sync_transcoders = 0; - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", encoder->base.base.id, encoder->base.name, crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); @@ -4623,7 +4596,7 @@ static const struct drm_encoder_funcs intel_ddi_funcs = { static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); struct intel_connector *connector; enum port port = dig_port->base.port; @@ -4632,7 +4605,7 @@ static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) return -ENOMEM; dig_port->dp.output_reg = DDI_BUF_CTL(port); - if (DISPLAY_VER(i915) >= 14) + if (DISPLAY_VER(display) >= 14) dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; else dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; @@ -4648,15 +4621,14 @@ static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) } if (dig_port->base.type == INTEL_OUTPUT_EDP) { - struct drm_device *dev = dig_port->base.base.dev; struct drm_privacy_screen *privacy_screen; - privacy_screen = drm_privacy_screen_get(dev->dev, NULL); + privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); if (!IS_ERR(privacy_screen)) { drm_connector_attach_privacy_screen_provider(&connector->base, privacy_screen); } else if (PTR_ERR(privacy_screen) != -ENODEV) { - drm_warn(dev, "Error getting privacy-screen\n"); + drm_warn(display->drm, "Error getting privacy-screen\n"); } } @@ -4667,7 +4639,6 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); struct intel_connector *connector = hdmi->attached_connector; struct i2c_adapter *ddc = connector->base.ddc; @@ -4680,7 +4651,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, if (connector->base.status != connector_status_connected) return 0; - ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, + ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, ctx); if (ret) return ret; @@ -4697,7 +4668,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, crtc_state = to_intel_crtc_state(crtc->base.state); - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(display->drm, !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); if (!crtc_state->hw.active) @@ -4713,7 +4684,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); if (ret < 0) { - drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", + drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", connector->base.base.id, connector->base.name, ret); return 0; } @@ -4738,11 +4709,11 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, static void intel_ddi_link_check(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); /* TODO: Move checking the HDMI link state here as well. */ - drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); + drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); intel_dp_link_check(encoder); } @@ -4805,26 +4776,26 @@ intel_ddi_hotplug(struct intel_encoder *encoder, static bool lpt_digital_port_connected(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; + struct intel_display *display = to_intel_display(encoder); + u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; - return intel_de_read(dev_priv, SDEISR) & bit; + return intel_de_read(display, SDEISR) & bit; } static bool hsw_digital_port_connected(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; + struct intel_display *display = to_intel_display(encoder); + u32 bit = display->hotplug.hpd[encoder->hpd_pin]; - return intel_de_read(dev_priv, DEISR) & bit; + return intel_de_read(display, DEISR) & bit; } static bool bdw_digital_port_connected(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; + struct intel_display *display = to_intel_display(encoder); + u32 bit = display->hotplug.hpd[encoder->hpd_pin]; - return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; + return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; } static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) @@ -4853,7 +4824,7 @@ static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) { - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); if (dig_port->base.port != PORT_A) return false; @@ -4864,7 +4835,7 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only * supported configuration */ - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (display->platform.geminilake || display->platform.broxton) return true; return false; @@ -4873,15 +4844,15 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) static int intel_ddi_max_lanes(struct intel_digital_port *dig_port) { - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); enum port port = dig_port->base.port; int max_lanes = 4; - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) return max_lanes; if (port == PORT_A || port == PORT_E) { - if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) + if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) max_lanes = port == PORT_A ? 4 : 0; else /* Both A and E share 2 lanes */ @@ -4894,7 +4865,7 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port) * so we use the proper lane count for our calculations. */ if (intel_ddi_a_force_4_lanes(dig_port)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Forcing DDI_A_4_LANES for port A\n"); dig_port->ddi_a_4_lanes = true; max_lanes = 4; @@ -4903,8 +4874,7 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port) return max_lanes; } -static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) { if (port >= PORT_D_XELPD) return HPD_PORT_D + port - PORT_D_XELPD; @@ -4914,8 +4884,7 @@ static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) { if (port >= PORT_TC1) return HPD_PORT_C + port - PORT_TC1; @@ -4923,8 +4892,7 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) { if (port >= PORT_TC1) return HPD_PORT_TC1 + port - PORT_TC1; @@ -4932,11 +4900,12 @@ static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + if (HAS_PCH_TGP(dev_priv)) - return tgl_hpd_pin(dev_priv, port); + return tgl_hpd_pin(display, port); if (port >= PORT_TC1) return HPD_PORT_C + port - PORT_TC1; @@ -4944,8 +4913,7 @@ static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) { if (port >= PORT_C) return HPD_PORT_TC1 + port - PORT_C; @@ -4953,31 +4921,34 @@ static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + if (port == PORT_D) return HPD_PORT_A; if (HAS_PCH_TGP(dev_priv)) - return icl_hpd_pin(dev_priv, port); + return icl_hpd_pin(display, port); return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) +static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + if (HAS_PCH_TGP(dev_priv)) - return icl_hpd_pin(dev_priv, port); + return icl_hpd_pin(display, port); return HPD_PORT_A + port - PORT_A; } -static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) +static bool intel_ddi_is_tc(struct intel_display *display, enum port port) { - if (DISPLAY_VER(i915) >= 12) + if (DISPLAY_VER(display) >= 12) return port >= PORT_TC1; - else if (DISPLAY_VER(i915) >= 11) + else if (DISPLAY_VER(display) >= 11) return port >= PORT_C; else return false; @@ -5020,21 +4991,21 @@ static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder #define port_tc_name(port) ((port) - PORT_TC1 + '1') #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') -static bool port_strap_detected(struct drm_i915_private *i915, enum port port) +static bool port_strap_detected(struct intel_display *display, enum port port) { /* straps not used on skl+ */ - if (DISPLAY_VER(i915) >= 9) + if (DISPLAY_VER(display) >= 9) return true; switch (port) { case PORT_A: - return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; + return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; case PORT_B: - return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; + return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; case PORT_C: - return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; + return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; case PORT_D: - return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; + return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; case PORT_E: return true; /* no strap for DDI-E */ default: @@ -5048,18 +5019,18 @@ static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) return init_dp || intel_encoder_is_tc(encoder); } -static bool assert_has_icl_dsi(struct drm_i915_private *i915) +static bool assert_has_icl_dsi(struct intel_display *display) { - return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && - !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, + return !drm_WARN(display->drm, !display->platform.alderlake_p && + !display->platform.tigerlake && DISPLAY_VER(display) != 11, "Platform does not support DSI\n"); } -static bool port_in_use(struct drm_i915_private *i915, enum port port) +static bool port_in_use(struct intel_display *display, enum port port) { struct intel_encoder *encoder; - for_each_intel_encoder(&i915->drm, encoder) { + for_each_intel_encoder(display->drm, encoder) { /* FIXME what about second port for dual link DSI? */ if (encoder->port == port) return true; @@ -5071,7 +5042,6 @@ static bool port_in_use(struct drm_i915_private *i915, enum port port) void intel_ddi_init(struct intel_display *display, const struct intel_bios_encoder_data *devdata) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port; struct intel_encoder *encoder; bool init_hdmi, init_dp; @@ -5083,8 +5053,8 @@ void intel_ddi_init(struct intel_display *display, if (port == PORT_NONE) return; - if (!port_strap_detected(dev_priv, port)) { - drm_dbg_kms(&dev_priv->drm, + if (!port_strap_detected(display, port)) { + drm_dbg_kms(display->drm, "Port %c strap not detected\n", port_name(port)); return; } @@ -5092,15 +5062,15 @@ void intel_ddi_init(struct intel_display *display, if (!assert_port_valid(display, port)) return; - if (port_in_use(dev_priv, port)) { - drm_dbg_kms(&dev_priv->drm, + if (port_in_use(display, port)) { + drm_dbg_kms(display->drm, "Port %c already claimed\n", port_name(port)); return; } if (intel_bios_encoder_supports_dsi(devdata)) { /* BXT/GLK handled elsewhere, for now at least */ - if (!assert_has_icl_dsi(dev_priv)) + if (!assert_has_icl_dsi(display)) return; icl_dsi_init(display, devdata); @@ -5116,7 +5086,7 @@ void intel_ddi_init(struct intel_display *display, * outputs. */ if (intel_hti_uses_phy(display, phy)) { - drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", + drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", port_name(port), phy_name(phy)); return; } @@ -5133,20 +5103,20 @@ void intel_ddi_init(struct intel_display *display, */ init_dp = true; init_hdmi = false; - drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", + drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", port_name(port)); } if (!init_dp && !init_hdmi) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", port_name(port)); return; } if (intel_phy_is_snps(display, phy) && - dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { - drm_dbg_kms(&dev_priv->drm, + display->snps.phy_failed_calibration & BIT(phy)) { + drm_dbg_kms(display->drm, "SNPS PHY %c failed to calibrate, proceeding anyway\n", phy_name(phy)); } @@ -5160,26 +5130,26 @@ void intel_ddi_init(struct intel_display *display, encoder = &dig_port->base; encoder->devdata = devdata; - if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { - drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, + if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { + drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %c/PHY %c", port_name(port - PORT_D_XELPD + PORT_D), phy_name(phy)); - } else if (DISPLAY_VER(dev_priv) >= 12) { + } else if (DISPLAY_VER(display) >= 12) { enum tc_port tc_port = intel_port_to_tc(display, port); - drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, + drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %s%c/PHY %s%c", port >= PORT_TC1 ? "TC" : "", port >= PORT_TC1 ? port_tc_name(port) : port_name(port), tc_port != TC_PORT_NONE ? "TC" : "", tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); - } else if (DISPLAY_VER(dev_priv) >= 11) { + } else if (DISPLAY_VER(display) >= 11) { enum tc_port tc_port = intel_port_to_tc(display, port); - drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, + drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %c%s/PHY %s%c", port_name(port), @@ -5187,7 +5157,7 @@ void intel_ddi_init(struct intel_display *display, tc_port != TC_PORT_NONE ? "TC" : "", tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); } else { - drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, + drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %c/PHY %c", port_name(port), phy_name(phy)); } @@ -5223,32 +5193,32 @@ void intel_ddi_init(struct intel_display *display, encoder->cloneable = 0; encoder->pipe_mask = ~0; - if (DISPLAY_VER(dev_priv) >= 14) { + if (DISPLAY_VER(display) >= 14) { encoder->enable_clock = intel_mtl_pll_enable; encoder->disable_clock = intel_mtl_pll_disable; encoder->port_pll_type = intel_mtl_port_pll_type; encoder->get_config = mtl_ddi_get_config; - } else if (IS_DG2(dev_priv)) { + } else if (display->platform.dg2) { encoder->enable_clock = intel_mpllb_enable; encoder->disable_clock = intel_mpllb_disable; encoder->get_config = dg2_ddi_get_config; - } else if (IS_ALDERLAKE_S(dev_priv)) { + } else if (display->platform.alderlake_s) { encoder->enable_clock = adls_ddi_enable_clock; encoder->disable_clock = adls_ddi_disable_clock; encoder->is_clock_enabled = adls_ddi_is_clock_enabled; encoder->get_config = adls_ddi_get_config; - } else if (IS_ROCKETLAKE(dev_priv)) { + } else if (display->platform.rocketlake) { encoder->enable_clock = rkl_ddi_enable_clock; encoder->disable_clock = rkl_ddi_disable_clock; encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; encoder->get_config = rkl_ddi_get_config; - } else if (IS_DG1(dev_priv)) { + } else if (display->platform.dg1) { encoder->enable_clock = dg1_ddi_enable_clock; encoder->disable_clock = dg1_ddi_disable_clock; encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; encoder->get_config = dg1_ddi_get_config; - } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { - if (intel_ddi_is_tc(dev_priv, port)) { + } else if (display->platform.jasperlake || display->platform.elkhartlake) { + if (intel_ddi_is_tc(display, port)) { encoder->enable_clock = jsl_ddi_tc_enable_clock; encoder->disable_clock = jsl_ddi_tc_disable_clock; encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; @@ -5260,8 +5230,8 @@ void intel_ddi_init(struct intel_display *display, encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; encoder->get_config = icl_ddi_combo_get_config; } - } else if (DISPLAY_VER(dev_priv) >= 11) { - if (intel_ddi_is_tc(dev_priv, port)) { + } else if (DISPLAY_VER(display) >= 11) { + if (intel_ddi_is_tc(display, port)) { encoder->enable_clock = icl_ddi_tc_enable_clock; encoder->disable_clock = icl_ddi_tc_disable_clock; encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; @@ -5273,36 +5243,36 @@ void intel_ddi_init(struct intel_display *display, encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; encoder->get_config = icl_ddi_combo_get_config; } - } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { + } else if (display->platform.geminilake || display->platform.broxton) { /* BXT/GLK have fixed PLL->port mapping */ encoder->get_config = bxt_ddi_get_config; - } else if (DISPLAY_VER(dev_priv) == 9) { + } else if (DISPLAY_VER(display) == 9) { encoder->enable_clock = skl_ddi_enable_clock; encoder->disable_clock = skl_ddi_disable_clock; encoder->is_clock_enabled = skl_ddi_is_clock_enabled; encoder->get_config = skl_ddi_get_config; - } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + } else if (display->platform.broadwell || display->platform.haswell) { encoder->enable_clock = hsw_ddi_enable_clock; encoder->disable_clock = hsw_ddi_disable_clock; encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; encoder->get_config = hsw_ddi_get_config; } - if (DISPLAY_VER(dev_priv) >= 14) { + if (DISPLAY_VER(display) >= 14) { encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; - } else if (IS_DG2(dev_priv)) { + } else if (display->platform.dg2) { encoder->set_signal_levels = intel_snps_phy_set_signal_levels; - } else if (DISPLAY_VER(dev_priv) >= 12) { + } else if (DISPLAY_VER(display) >= 12) { if (intel_encoder_is_combo(encoder)) encoder->set_signal_levels = icl_combo_phy_set_signal_levels; else encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; - } else if (DISPLAY_VER(dev_priv) >= 11) { + } else if (DISPLAY_VER(display) >= 11) { if (intel_encoder_is_combo(encoder)) encoder->set_signal_levels = icl_combo_phy_set_signal_levels; else encoder->set_signal_levels = icl_mg_phy_set_signal_levels; - } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { + } else if (display->platform.geminilake || display->platform.broxton) { encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; } else { encoder->set_signal_levels = hsw_set_signal_levels; @@ -5310,29 +5280,29 @@ void intel_ddi_init(struct intel_display *display, intel_ddi_buf_trans_init(encoder); - if (DISPLAY_VER(dev_priv) >= 13) - encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); - else if (IS_DG1(dev_priv)) - encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); - else if (IS_ROCKETLAKE(dev_priv)) - encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); - else if (DISPLAY_VER(dev_priv) >= 12) - encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); - else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) - encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); - else if (DISPLAY_VER(dev_priv) == 11) - encoder->hpd_pin = icl_hpd_pin(dev_priv, port); - else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) - encoder->hpd_pin = skl_hpd_pin(dev_priv, port); + if (DISPLAY_VER(display) >= 13) + encoder->hpd_pin = xelpd_hpd_pin(display, port); + else if (display->platform.dg1) + encoder->hpd_pin = dg1_hpd_pin(display, port); + else if (display->platform.rocketlake) + encoder->hpd_pin = rkl_hpd_pin(display, port); + else if (DISPLAY_VER(display) >= 12) + encoder->hpd_pin = tgl_hpd_pin(display, port); + else if (display->platform.jasperlake || display->platform.elkhartlake) + encoder->hpd_pin = ehl_hpd_pin(display, port); + else if (DISPLAY_VER(display) == 11) + encoder->hpd_pin = icl_hpd_pin(display, port); + else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) + encoder->hpd_pin = skl_hpd_pin(display, port); else encoder->hpd_pin = intel_hpd_pin_default(port); - ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); + ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; - dig_port->ddi_a_4_lanes = DISPLAY_VER(dev_priv) < 11 && ddi_buf_ctl & DDI_A_4_LANES; + dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; dig_port->dp.output_reg = INVALID_MMIO_REG; dig_port->max_lanes = intel_ddi_max_lanes(dig_port); @@ -5351,7 +5321,7 @@ void intel_ddi_init(struct intel_display *display, if (!is_legacy && init_hdmi) { is_legacy = !init_dp; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", port_name(port), str_yes_no(init_dp), @@ -5368,24 +5338,24 @@ void intel_ddi_init(struct intel_display *display, goto err; } - drm_WARN_ON(&dev_priv->drm, port > PORT_I); + drm_WARN_ON(display->drm, port > PORT_I); dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); - if (DISPLAY_VER(dev_priv) >= 11) { + if (DISPLAY_VER(display) >= 11) { if (intel_encoder_is_tc(encoder)) dig_port->connected = intel_tc_port_connected; else dig_port->connected = lpt_digital_port_connected; - } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { + } else if (display->platform.geminilake || display->platform.broxton) { dig_port->connected = bdw_digital_port_connected; - } else if (DISPLAY_VER(dev_priv) == 9) { + } else if (DISPLAY_VER(display) == 9) { dig_port->connected = lpt_digital_port_connected; - } else if (IS_BROADWELL(dev_priv)) { + } else if (display->platform.broadwell) { if (port == PORT_A) dig_port->connected = bdw_digital_port_connected; else dig_port->connected = lpt_digital_port_connected; - } else if (IS_HASWELL(dev_priv)) { + } else if (display->platform.haswell) { if (port == PORT_A) dig_port->connected = hsw_digital_port_connected; else @@ -5401,7 +5371,7 @@ void intel_ddi_init(struct intel_display *display, dig_port->hpd_pulse = intel_dp_hpd_pulse; if (dig_port->dp.mso_link_count) - encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); + encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); } /* -- 2.51.0