From f67f8c61b7fd3f72cf716b3845211e69265d13bd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Feb 2025 15:43:21 +0100 Subject: [PATCH 01/16] dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints (Almost?) all QMP PHYs come with both a "full reset" ("phy") and a "retain certain registers" one ("phy_nocsr"). Drop the maxItems=1 constraint for resets and reset_names as we go ahead and straighten out the DT usage. After that's done (which will involve modifying some clock drivers etc.), we may set *min*Items to 2, bar some possible exceptions. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-2-72cd4cdc767b@oss.qualcomm.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 ------ 1 file changed, 6 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 51eaffa45c18..af8c4aa4f43d 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -220,12 +220,6 @@ allOf: minItems: 2 reset-names: minItems: 2 - else: - properties: - resets: - maxItems: 1 - reset-names: - maxItems: 1 - if: properties: -- 2.51.0 From 0d8db251dd15d2e284f5a6a53bc2b869f3eca711 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Feb 2025 15:43:22 +0100 Subject: [PATCH 02/16] phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY Add a new, common configuration for Gen4x4 V6 PHYs without an init sequence. The bootloader configures the hardware once and the OS retains that configuration by using the NOCSR reset line (which doesn't drop register state on assert) in place of the "full reset" one. Use this new configuration for X1P42100's Gen4x4 PHY. Acked-by: Dmitry Baryshkov Tested-by: Jens Glathe Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-3-72cd4cdc767b@oss.qualcomm.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 018bbb300830..6726bbe4ad15 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4156,6 +4156,21 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { .has_nocsr_reset = true, }; +static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = { + .lanes = 4, + + .offsets = &qmp_pcie_offsets_v6_20, + + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = pciephy_v6_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, +}; + static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) { const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -4960,6 +4975,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy", .data = &x1e80100_qmp_gen4x8_pciephy_cfg, + }, { + .compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy", + .data = &qmp_v6_gen4x4_pciephy_cfg, }, { }, }; -- 2.51.0 From d02dfd4ceb2e9f34caaaaf87105267e2f722f443 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 3 Feb 2025 12:54:21 -0600 Subject: [PATCH 03/16] phy: can-transceiver: Drop unnecessary "mux-states" property presence check It doesn't matter whether "mux-states" is not present or there is some other issue parsing it causing an error. Drop the presence check and rework the error handling to ignore anything other than deferred probe. Acked-by: Marc Kleine-Budde Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250203185421.3383805-2-robh@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/phy-can-transceiver.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/phy/phy-can-transceiver.c b/drivers/phy/phy-can-transceiver.c index ee4ce4249698..2bec70615449 100644 --- a/drivers/phy/phy-can-transceiver.c +++ b/drivers/phy/phy-can-transceiver.c @@ -103,6 +103,7 @@ static int can_transceiver_phy_probe(struct platform_device *pdev) struct phy *phy; struct gpio_desc *standby_gpio; struct gpio_desc *enable_gpio; + struct mux_state *mux_state; u32 max_bitrate = 0; int err; @@ -113,13 +114,11 @@ static int can_transceiver_phy_probe(struct platform_device *pdev) match = of_match_node(can_transceiver_phy_ids, pdev->dev.of_node); drvdata = match->data; - if (of_property_read_bool(dev->of_node, "mux-states")) { - struct mux_state *mux_state; - - mux_state = devm_mux_state_get(dev, NULL); - if (IS_ERR(mux_state)) - return dev_err_probe(&pdev->dev, PTR_ERR(mux_state), - "failed to get mux\n"); + mux_state = devm_mux_state_get(dev, NULL); + if (IS_ERR(mux_state)) { + if (PTR_ERR(mux_state) == -EPROBE_DEFER) + return PTR_ERR(mux_state); + } else { can_transceiver_phy->mux_state = mux_state; } -- 2.51.0 From 88c0053baed659acd85b87dd52cbd75f3d8806be Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 31 Dec 2024 10:31:20 -0600 Subject: [PATCH 04/16] phy: Use (of|device)_property_present() for non-boolean properties The use of (of|device)_property_read_bool() for non-boolean properties is deprecated in favor of (of|device)_property_present() when testing for property presence. Signed-off-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chunfeng Yun Link: https://lore.kernel.org/r/20241231163121.241543-1-robh@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-tphy.c | 4 ++-- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index a496fbe3352b..644a34bd2b0b 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -1195,7 +1195,7 @@ static int phy_type_syscon_get(struct mtk_phy_instance *instance, int ret; /* type switch function is optional */ - if (!of_property_read_bool(dn, "mediatek,syscon-type")) + if (!of_property_present(dn, "mediatek,syscon-type")) return 0; ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type", @@ -1258,7 +1258,7 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc } /* software efuse is optional */ - instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells"); + instance->efuse_sw_en = device_property_present(dev, "nvmem-cells"); if (!instance->efuse_sw_en) return 0; diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 96f3d868a526..b5e6a864deeb 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -440,7 +440,7 @@ static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy) struct extcon_dev *edev; int ret; - if (of_property_read_bool(node, "extcon")) { + if (of_property_present(node, "extcon")) { edev = extcon_get_edev_by_phandle(rphy->dev, 0); if (IS_ERR(edev)) return dev_err_probe(rphy->dev, PTR_ERR(edev), @@ -1323,7 +1323,7 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, goto out; } - if (!of_property_read_bool(rphy->dev->of_node, "extcon")) { + if (!of_property_present(rphy->dev->of_node, "extcon")) { /* do initial sync of usb state */ id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id); -- 2.51.0 From 642b1ed4cd184d5c2e5814c220bb93453492644d Mon Sep 17 00:00:00 2001 From: =?utf8?q?Andr=C3=A9=20Draszik?= Date: Fri, 6 Dec 2024 16:31:01 +0000 Subject: [PATCH 05/16] dt-bindings: phy: samsung,usb3-drd-phy: add blank lines between DT properties MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit In [1], Rob pointed out that we should really be separating properties with blank lines in between, which is universal style. Only where properties are booleans, empty lines are not required. Do so. Link: https://lore.kernel.org/all/20240711212359.GA3023490-robh@kernel.org/ [1] Reviewed-by: Peter Griffin Acked-by: Rob Herring (Arm) Signed-off-by: André Draszik Tested-by: Will McVicker Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-1-f5961268b149@linaro.org Signed-off-by: Vinod Koul --- .../bindings/phy/samsung,usb3-drd-phy.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 16321cdd4919..1f8b35917b11 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -83,14 +83,19 @@ properties: pll-supply: description: Power supply for the USB PLL. + dvdd-usb20-supply: description: DVDD power supply for the USB 2.0 phy. + vddh-usb20-supply: description: VDDh power supply for the USB 2.0 phy. + vdd33-usb20-supply: description: 3.3V power supply for the USB 2.0 phy. + vdda-usbdp-supply: description: VDDa power supply for the USB DP phy. + vddh-usbdp-supply: description: VDDh power supply for the USB DP phy. @@ -117,6 +122,7 @@ allOf: - description: Gate of control interface AXI clock - description: Gate of control interface APB clock - description: Gate of SCL APB clock + clock-names: items: - const: phy @@ -124,10 +130,13 @@ allOf: - const: ctrl_aclk - const: ctrl_pclk - const: scl_pclk + reg: minItems: 3 + reg-names: minItems: 3 + required: - reg-names - pll-supply @@ -149,6 +158,7 @@ allOf: clocks: minItems: 5 maxItems: 5 + clock-names: items: - const: phy @@ -156,8 +166,10 @@ allOf: - const: phy_utmi - const: phy_pipe - const: itp + reg: maxItems: 1 + reg-names: maxItems: 1 @@ -174,12 +186,15 @@ allOf: clocks: minItems: 2 maxItems: 2 + clock-names: items: - const: phy - const: ref + reg: maxItems: 1 + reg-names: maxItems: 1 -- 2.51.0 From c38528812c2e9b05fe8b5fd1f66cf4c75835a38e Mon Sep 17 00:00:00 2001 From: =?utf8?q?Andr=C3=A9=20Draszik?= Date: Fri, 6 Dec 2024 16:31:02 +0000 Subject: [PATCH 06/16] dt-bindings: phy: samsung,usb3-drd-phy: gs101: require Type-C properties MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit orientation-switch is the standard declaration to inform the Type-C mux layer that a remote-endpoint is capable of processing orientation change messages. The USB PHY on gs101 needs to be configured based on the orientation of the connector. For that the DTS needs a link between the phy's port and a TCPCi, and we'll need to inform the phy driver that it should handle the orientation (register a handler). Update the schema to enforce that by requiring the orientation-switch and port properties on gs101 (only). We disallow orientation-switch on all other supported platforms, since other versions of this phy (or its system integration) don't currently support or even need it. Even though this new required gs101 property is an ABI break, the intention for the driver is to behave as before if it's missing (meaning for gs101 it will work in SS mode in one orientation only). Other platforms are not affected. Reviewed-by: Peter Griffin Signed-off-by: André Draszik Reviewed-by: Rob Herring (Arm) Tested-by: Will McVicker Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-2-f5961268b149@linaro.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 1f8b35917b11..27295acbba76 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -114,6 +114,8 @@ allOf: contains: const: google,gs101-usb31drd-phy then: + $ref: /schemas/usb/usb-switch.yaml# + properties: clocks: items: @@ -139,6 +141,8 @@ allOf: required: - reg-names + - orientation-switch + - port - pll-supply - dvdd-usb20-supply - vddh-usb20-supply @@ -198,7 +202,7 @@ allOf: reg-names: maxItems: 1 -additionalProperties: false +unevaluatedProperties: false examples: - | -- 2.51.0 From ee064390b82329df7fd8e0c48da03a8fee7d46ce Mon Sep 17 00:00:00 2001 From: =?utf8?q?Andr=C3=A9=20Draszik?= Date: Fri, 6 Dec 2024 16:31:03 +0000 Subject: [PATCH 07/16] phy: exynos5-usbdrd: convert to dev_err_probe MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit dev_err_probe() exists to simplify code. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Peter Griffin Signed-off-by: André Draszik Tested-by: Will McVicker Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-3-f5961268b149@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index c421b495eb0f..ceae4b47cece 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1725,10 +1725,9 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "samsung,pmu-syscon"); - if (IS_ERR(reg_pmu)) { - dev_err(dev, "Failed to lookup PMU regmap\n"); - return PTR_ERR(reg_pmu); - } + if (IS_ERR(reg_pmu)) + return dev_err_probe(dev, PTR_ERR(reg_pmu), + "Failed to lookup PMU regmap\n"); /* * Exynos5420 SoC has multiple channels for USB 3.0 PHY, with @@ -1759,10 +1758,9 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) { struct phy *phy = devm_phy_create(dev, NULL, drv_data->phy_ops); - if (IS_ERR(phy)) { - dev_err(dev, "Failed to create usbdrd_phy phy\n"); - return PTR_ERR(phy); - } + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), + "Failed to create usbdrd_phy phy\n"); phy_drd->phys[i].phy = phy; phy_drd->phys[i].index = i; @@ -1786,10 +1784,9 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) phy_provider = devm_of_phy_provider_register(dev, exynos5_usbdrd_phy_xlate); - if (IS_ERR(phy_provider)) { - dev_err(phy_drd->dev, "Failed to register phy provider\n"); - return PTR_ERR(phy_provider); - } + if (IS_ERR(phy_provider)) + return dev_err_probe(phy_drd->dev, PTR_ERR(phy_provider), + "Failed to register phy provider\n"); return 0; } -- 2.51.0 From 21860f340ba76ee042e5431ff92537f89bc11476 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Andr=C3=A9=20Draszik?= Date: Fri, 6 Dec 2024 16:31:04 +0000 Subject: [PATCH 08/16] phy: exynos5-usbdrd: fix EDS distribution tuning (gs101) MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This code's intention is to configure lane0 and lane2 tunings, but for lane2 there is a typo and it ends up tuning something else. Fix the typo, as it doesn't appear to make sense to apply different tunings for lane0 vs lane2. The same typo appears to exist in the bootloader, hence we restore the original value in the typo'd registers as well. This can be removed once / if the bootloader is updated. Note that this is incorrect in the downstream driver as well - the values had been copied from there. Reviewed-by: Peter Griffin Tested-by: Peter Griffin Signed-off-by: André Draszik Tested-by: Will McVicker Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-4-f5961268b149@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index ceae4b47cece..2a724d362c2d 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1510,8 +1510,11 @@ static const struct exynos5_usbdrd_phy_tuning gs101_tunes_pipe3_preinit[] = { PHY_TUNING_ENTRY_PMA(0x09e0, -1, 0x00), PHY_TUNING_ENTRY_PMA(0x09e4, -1, 0x36), PHY_TUNING_ENTRY_PMA(0x1e7c, -1, 0x06), - PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x00), - PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x36), + PHY_TUNING_ENTRY_PMA(0x19e0, -1, 0x00), + PHY_TUNING_ENTRY_PMA(0x19e4, -1, 0x36), + /* fix bootloader bug */ + PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x02), + PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x0b), /* improve LVCC */ PHY_TUNING_ENTRY_PMA(0x08f0, -1, 0x30), PHY_TUNING_ENTRY_PMA(0x18f0, -1, 0x30), -- 2.51.0 From 0bccdcb3eea93e087887027ff374dac5c3de36cd Mon Sep 17 00:00:00 2001 From: =?utf8?q?Andr=C3=A9=20Draszik?= Date: Fri, 6 Dec 2024 16:31:05 +0000 Subject: [PATCH 09/16] phy: exynos5-usbdrd: gs101: configure SS lanes based on orientation MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit USB SS lanes need to be configured based on the connector orientation - at most two lanes will be in use for USB (and the remaining two for alternate modes like DP). For the USB link to come up in SS, the lane configuration registers have to be programmed accordingly. While we still need a way to be notified of the actual connector orientation and then reprogram the registers accordingly (at the moment the configuration happens just once during phy_init() and never again), we can prepare the code doing the configuration to take the orientation into account. Do so. Note: the mutex is needed to synchronize this with the upcoming connector orientation callback. Reviewed-by: Peter Griffin Tested-by: Peter Griffin Signed-off-by: André Draszik Tested-by: Will McVicker Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-5-f5961268b149@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 72 +++++++++++++++++------- 1 file changed, 51 insertions(+), 21 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 2a724d362c2d..61e0de4b3d4b 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -23,6 +23,7 @@ #include #include #include +#include /* Exynos USB PHY registers */ #define EXYNOS5_FSEL_9MHZ6 0x0 @@ -209,6 +210,10 @@ #define EXYNOS9_PMA_USBDP_CMN_REG00B8 0x02e0 #define CMN_REG00B8_LANE_MUX_SEL_DP GENMASK(3, 0) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE3 BIT(3) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE2 BIT(2) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE1 BIT(1) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE0 BIT(0) #define EXYNOS9_PMA_USBDP_CMN_REG01C0 0x0700 #define CMN_REG01C0_ANA_LCPLL_LOCK_DONE BIT(7) @@ -383,11 +388,13 @@ struct exynos5_usbdrd_phy_drvdata { * @clks: clocks for register access * @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required) * @drv_data: pointer to SoC level driver data structure + * @phy_mutex: mutex protecting phy_init/exit & TCPC callbacks * @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY * instances each with its 'phy' and 'phy_cfg'. * @extrefclk: frequency select settings when using 'separate * reference clocks' for SS and HS operations * @regulators: regulators for phy + * @orientation: TypeC connector orientation - normal or flipped */ struct exynos5_usbdrd_phy { struct device *dev; @@ -397,6 +404,7 @@ struct exynos5_usbdrd_phy { struct clk_bulk_data *clks; struct clk_bulk_data *core_clks; const struct exynos5_usbdrd_phy_drvdata *drv_data; + struct mutex phy_mutex; struct phy_usb_instance { struct phy *phy; u32 index; @@ -406,6 +414,8 @@ struct exynos5_usbdrd_phy { } phys[EXYNOS5_DRDPHYS_NUM]; u32 extrefclk; struct regulator_bulk_data *regulators; + + enum typec_orientation orientation; }; static inline @@ -647,22 +657,38 @@ exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel(struct exynos5_usbdrd_phy *phy_drd) /* lane configuration: USB on all lanes */ reg = readl(regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8); reg &= ~CMN_REG00B8_LANE_MUX_SEL_DP; - writel(reg, regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8); - /* - * FIXME: below code supports one connector orientation only. It needs - * updating once we can receive connector events. + * USB on lanes 0 & 1 in normal mode, or 2 & 3 if reversed, DP on the + * other ones. */ + reg |= FIELD_PREP(CMN_REG00B8_LANE_MUX_SEL_DP, + ((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) + ? (CMN_REG00B8_LANE_MUX_SEL_DP_LANE3 + | CMN_REG00B8_LANE_MUX_SEL_DP_LANE2) + : (CMN_REG00B8_LANE_MUX_SEL_DP_LANE1 + | CMN_REG00B8_LANE_MUX_SEL_DP_LANE0))); + writel(reg, regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8); + /* override of TX receiver detector and comparator: lane 1 */ reg = readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413); - reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN; - reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_EN; + if (phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) { + reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN; + reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_EN; + } else { + reg |= TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN; + reg |= TRSV_REG0413_OVRD_LN1_TX_RXD_EN; + } writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413); /* lane 3 */ reg = readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813); - reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN; - reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_EN; + if (phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) { + reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN; + reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_EN; + } else { + reg &= ~TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN; + reg &= ~TRSV_REG0813_OVRD_LN3_TX_RXD_EN; + } writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813); } @@ -700,21 +726,18 @@ exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock(struct exynos5_usbdrd_phy *phy_drd int err; err = readl_poll_timeout( - phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG03C3, - reg, (reg & locked) == locked, sleep_us, timeout_us); - if (!err) - return; - - dev_err(phy_drd->dev, - "timed out waiting for CDR lock (l0): %#.8x, retrying\n", reg); - - /* based on cable orientation, this might be on the other phy port */ - err = readl_poll_timeout( - phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG07C3, + /* lane depends on cable orientation */ + (phy_drd->reg_pma + + ((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) + ? EXYNOS9_PMA_USBDP_TRSV_REG03C3 + : EXYNOS9_PMA_USBDP_TRSV_REG07C3)), reg, (reg & locked) == locked, sleep_us, timeout_us); if (err) dev_err(phy_drd->dev, - "timed out waiting for CDR lock (l2): %#.8x\n", reg); + "timed out waiting for CDR(l%d) lock: %#.8x\n", + ((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) + ? 0 + : 2), reg); } static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) @@ -1184,7 +1207,8 @@ static int exynos850_usbdrd_phy_init(struct phy *phy) return ret; /* UTMI or PIPE3 specific init */ - inst->phy_cfg->phy_init(phy_drd); + scoped_guard(mutex, &phy_drd->phy_mutex) + inst->phy_cfg->phy_init(phy_drd); clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); @@ -1203,6 +1227,8 @@ static int exynos850_usbdrd_phy_exit(struct phy *phy) if (ret) return ret; + guard(mutex)(&phy_drd->phy_mutex); + /* Set PHY clock and control HS PHY */ reg = readl(regs_base + EXYNOS850_DRD_UTMI); reg &= ~(UTMI_DP_PULLDOWN | UTMI_DM_PULLDOWN); @@ -1698,6 +1724,10 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) return -EINVAL; phy_drd->drv_data = drv_data; + ret = devm_mutex_init(dev, &phy_drd->phy_mutex); + if (ret) + return ret; + if (of_property_present(dev->of_node, "reg-names")) { void __iomem *reg; -- 2.51.0 From 09dc674295a388e71192430b6f9c3c5cb0eb47da Mon Sep 17 00:00:00 2001 From: =?utf8?q?Andr=C3=A9=20Draszik?= Date: Fri, 6 Dec 2024 16:31:06 +0000 Subject: [PATCH 10/16] phy: exynos5-usbdrd: subscribe to orientation notifier if required MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit gs101's SS phy needs to be configured differently based on the connector orientation, as the SS link can only be established if the mux is configured correctly. The code to handle programming of the mux is in place already, this commit now adds the missing pieces to subscribe to the Type-C orientation switch event. Note that for this all to work we rely on the USB controller re-initialising us. It should invoke our .exit() upon cable unplug, and during cable plug we'll receive the orientation event after which we expect our .init() to be called. Above reinitialisation happens if the DWC3 controller can enter runtime suspend automatically. For the DWC3 driver, this is an opt-in: echo auto > /sys/devices/.../11110000.usb/power/control Once done, things work as long as the UDC is not bound as otherwise it stays busy because it doesn't cancel / stop outstanding TRBs. For now we have to manually unbind the UDC in that case: echo "" > sys/kernel/config/usb_gadget/.../UDC Note that if the orientation-switch property is missing from the DT, the code will behave as before this commit (meaning for gs101 it will work in SS mode in one orientation only). Other platforms are not affected either way. Signed-off-by: André Draszik Tested-by: Will McVicker Reviewed-by: Peter Griffin Tested-by: Peter Griffin Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-6-f5961268b149@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/samsung/Kconfig | 1 + drivers/phy/samsung/phy-exynos5-usbdrd.c | 56 ++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig index e2330b0894d6..7fba571c0e2b 100644 --- a/drivers/phy/samsung/Kconfig +++ b/drivers/phy/samsung/Kconfig @@ -81,6 +81,7 @@ config PHY_EXYNOS5_USBDRD tristate "Exynos5 SoC series USB DRD PHY driver" depends on (ARCH_EXYNOS && OF) || COMPILE_TEST depends on HAS_IOMEM + depends on TYPEC || (TYPEC=n && COMPILE_TEST) depends on USB_DWC3_EXYNOS select GENERIC_PHY select MFD_SYSCON diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 61e0de4b3d4b..8fc15847cfd8 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -24,6 +24,7 @@ #include #include #include +#include /* Exynos USB PHY registers */ #define EXYNOS5_FSEL_9MHZ6 0x0 @@ -394,6 +395,7 @@ struct exynos5_usbdrd_phy_drvdata { * @extrefclk: frequency select settings when using 'separate * reference clocks' for SS and HS operations * @regulators: regulators for phy + * @sw: TypeC orientation switch handle * @orientation: TypeC connector orientation - normal or flipped */ struct exynos5_usbdrd_phy { @@ -415,6 +417,7 @@ struct exynos5_usbdrd_phy { u32 extrefclk; struct regulator_bulk_data *regulators; + struct typec_switch_dev *sw; enum typec_orientation orientation; }; @@ -1397,6 +1400,55 @@ static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd) return 0; } +static int exynos5_usbdrd_orien_sw_set(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct exynos5_usbdrd_phy *phy_drd = typec_switch_get_drvdata(sw); + + scoped_guard(mutex, &phy_drd->phy_mutex) + phy_drd->orientation = orientation; + + return 0; +} + +static void exynos5_usbdrd_orien_switch_unregister(void *data) +{ + struct exynos5_usbdrd_phy *phy_drd = data; + + typec_switch_unregister(phy_drd->sw); +} + +static int exynos5_usbdrd_setup_notifiers(struct exynos5_usbdrd_phy *phy_drd) +{ + int ret; + + if (!IS_ENABLED(CONFIG_TYPEC)) + return 0; + + if (device_property_present(phy_drd->dev, "orientation-switch")) { + struct typec_switch_desc sw_desc = { }; + + sw_desc.drvdata = phy_drd; + sw_desc.fwnode = dev_fwnode(phy_drd->dev); + sw_desc.set = exynos5_usbdrd_orien_sw_set; + + phy_drd->sw = typec_switch_register(phy_drd->dev, &sw_desc); + if (IS_ERR(phy_drd->sw)) + return dev_err_probe(phy_drd->dev, + PTR_ERR(phy_drd->sw), + "Failed to register TypeC orientation switch\n"); + + ret = devm_add_action_or_reset(phy_drd->dev, + exynos5_usbdrd_orien_switch_unregister, + phy_drd); + if (ret) + return dev_err_probe(phy_drd->dev, ret, + "Failed to register TypeC orientation devm action\n"); + } + + return 0; +} + static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = { { .id = EXYNOS5_DRDPHY_UTMI, @@ -1786,6 +1838,10 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "failed to get regulators\n"); + ret = exynos5_usbdrd_setup_notifiers(phy_drd); + if (ret) + return ret; + dev_vdbg(dev, "Creating usbdrd_phy phy\n"); for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) { -- 2.51.0 From f4fb9c4d7f94dabef4abf2209cf840dd1c9ca11e Mon Sep 17 00:00:00 2001 From: =?utf8?q?Andr=C3=A9=20Draszik?= Date: Fri, 6 Dec 2024 16:31:07 +0000 Subject: [PATCH 11/16] phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+) MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit To make USB runtime suspend work when a UDC has been bound, the phy needs to inform the USBDRD controller (DWC3) that Vbus and bvalid are gone, so that it can in turn raise the respective gadget interrupt with event == DWC3_DEVICE_EVENT_DISCONNECT, which will cause the USB stack to clean up, allowing DWC3 to enter runtime suspend. On e850 and gs101 this isn't working, as the respective signals are not directly connected, and instead this driver uses override bits in the PHY IP to set those signals. It currently forcefully sets them to 'on', so the above mentioned interrupt will not be raised, preventing runtime suspend. To detect that state, update this driver to act on the TCPC's orientation signal - when orientation == NONE, Vbus is gone and we can clear the respective bits. Similarly, for other orientation values we re-enable them. This makes runtime suspend work on platforms with a TCPC (like Pixel6), while keeping compatibility with platforms without (e850-96). With runtime suspend working, USB-C cable orientation detection now also fully works on such platforms, and the link comes up as Superspeed as expected irrespective of the cable orientation and whether UDC / gadget are configured and active. Signed-off-by: André Draszik Tested-by: Will McVicker Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-7-f5961268b149@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 50 ++++++++++++++++++++---- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 8fc15847cfd8..bac1dc927b26 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1137,13 +1137,15 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) reg |= LINKCTRL_BUS_FILTER_BYPASS(0xf); writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); - reg = readl(regs_base + EXYNOS850_DRD_UTMI); - reg |= UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID; - writel(reg, regs_base + EXYNOS850_DRD_UTMI); - - reg = readl(regs_base + EXYNOS850_DRD_HSP); - reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; - writel(reg, regs_base + EXYNOS850_DRD_HSP); + if (!phy_drd->sw) { + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg |= UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID; + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + } reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL); reg &= ~SSPPLLCTL_FSEL; @@ -1404,9 +1406,41 @@ static int exynos5_usbdrd_orien_sw_set(struct typec_switch_dev *sw, enum typec_orientation orientation) { struct exynos5_usbdrd_phy *phy_drd = typec_switch_get_drvdata(sw); + int ret; + + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) { + dev_err(phy_drd->dev, "Failed to enable PHY clocks(s)\n"); + return ret; + } + + scoped_guard(mutex, &phy_drd->phy_mutex) { + void __iomem * const regs_base = phy_drd->reg_phy; + unsigned int reg; + + if (orientation == TYPEC_ORIENTATION_NONE) { + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg &= ~(UTMI_FORCE_VBUSVALID | UTMI_FORCE_BVALID); + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg |= HSP_VBUSVLDEXTSEL; + reg &= ~HSP_VBUSVLDEXT; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + } else { + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg |= UTMI_FORCE_VBUSVALID | UTMI_FORCE_BVALID; + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg |= HSP_VBUSVLDEXTSEL | HSP_VBUSVLDEXT; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + } - scoped_guard(mutex, &phy_drd->phy_mutex) phy_drd->orientation = orientation; + } + + clk_bulk_disable(phy_drd->drv_data->n_clks, phy_drd->clks); return 0; } -- 2.51.0 From 13c1eb1b4bd169f820188c62acaa1f96677284b1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 11 Jan 2025 19:54:07 +0100 Subject: [PATCH 12/16] phy: stih407-usb: Use syscon_regmap_lookup_by_phandle_args Use syscon_regmap_lookup_by_phandle_args() which is a wrapper over syscon_regmap_lookup_by_phandle() combined with getting the syscon argument. Except simpler code this annotates within one line that given phandle has arguments, so grepping for code would be easier. There is also no real benefit in printing errors on missing syscon argument, because this is done just too late: runtime check on static/build-time data. Dtschema and Devicetree bindings offer the static/build-time check for this already. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Patrice Chotard Link: https://lore.kernel.org/r/20250111185407.183855-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/st/phy-stih407-usb.c | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/drivers/phy/st/phy-stih407-usb.c b/drivers/phy/st/phy-stih407-usb.c index a4ae2cca7f63..ebb1d0858aa3 100644 --- a/drivers/phy/st/phy-stih407-usb.c +++ b/drivers/phy/st/phy-stih407-usb.c @@ -18,8 +18,8 @@ #include #include -#define PHYPARAM_REG 1 -#define PHYCTRL_REG 2 +#define PHYPARAM_REG 0 +#define PHYCTRL_REG 1 /* Default PHY_SEL and REFCLKSEL configuration */ #define STIH407_USB_PICOPHY_CTRL_PORT_CONF 0x6 @@ -91,8 +91,8 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct phy_provider *phy_provider; + unsigned int syscon_args[2]; struct phy *phy; - int ret; phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL); if (!phy_dev) @@ -116,25 +116,15 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev) /* Reset port by default: only deassert it in phy init */ reset_control_assert(phy_dev->rstport); - phy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); + phy_dev->regmap = syscon_regmap_lookup_by_phandle_args(np, "st,syscfg", + 2, syscon_args); if (IS_ERR(phy_dev->regmap)) { dev_err(dev, "No syscfg phandle specified\n"); return PTR_ERR(phy_dev->regmap); } - ret = of_property_read_u32_index(np, "st,syscfg", PHYPARAM_REG, - &phy_dev->param); - if (ret) { - dev_err(dev, "can't get phyparam offset (%d)\n", ret); - return ret; - } - - ret = of_property_read_u32_index(np, "st,syscfg", PHYCTRL_REG, - &phy_dev->ctrl); - if (ret) { - dev_err(dev, "can't get phyctrl offset (%d)\n", ret); - return ret; - } + phy_dev->param = syscon_args[PHYPARAM_REG]; + phy_dev->ctrl = syscon_args[PHYCTRL_REG]; phy = devm_phy_create(dev, NULL, &stih407_usb2_picophy_data); if (IS_ERR(phy)) { -- 2.51.0 From d58c04e305afbaa9dda7969151f06c4efe2c98b0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 9 Feb 2025 14:31:45 +0200 Subject: [PATCH 13/16] phy: core: don't require set_mode() callback for phy_get_mode() to work As reported by Damon Ding, the phy_get_mode() call doesn't work as expected unless the PHY driver has a .set_mode() call. This prompts PHY drivers to have empty stubs for .set_mode() for the sake of being able to get the mode. Make .set_mode() callback truly optional and update PHY's mode even if it there is none. Cc: Damon Ding Link: https://lore.kernel.org/r/96f8310f-93f1-4bcb-8637-137e1159ff83@rock-chips.com Tested-by: Damon Ding Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250209-phy-fix-set-moe-v2-1-76e248503856@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/phy-core.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index 8dfdce605a90..067316dfcd83 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -405,13 +405,14 @@ EXPORT_SYMBOL_GPL(phy_power_off); int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode) { - int ret; + int ret = 0; - if (!phy || !phy->ops->set_mode) + if (!phy) return 0; mutex_lock(&phy->mutex); - ret = phy->ops->set_mode(phy, mode, submode); + if (phy->ops->set_mode) + ret = phy->ops->set_mode(phy, mode, submode); if (!ret) phy->attrs.mode = mode; mutex_unlock(&phy->mutex); -- 2.51.0 From 279950205dde78bc0e3ca73a8dfee6842f0e1edc Mon Sep 17 00:00:00 2001 From: Pei Xiao Date: Sat, 8 Feb 2025 11:44:01 +0800 Subject: [PATCH 14/16] phy: freescale: fsl-samsung-hdmi: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly. Signed-off-by: Pei Xiao Link: https://lore.kernel.org/r/tencent_9087BCE04E38E6AA5C4B2252B82FA99C2009@qq.com Signed-off-by: Vinod Koul --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index 45004f598e4d..f0f2ed414db5 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -659,7 +659,7 @@ static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev) if (IS_ERR(phy->regs)) return PTR_ERR(phy->regs); - phy->apbclk = devm_clk_get(phy->dev, "apb"); + phy->apbclk = devm_clk_get_enabled(phy->dev, "apb"); if (IS_ERR(phy->apbclk)) return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk), "failed to get apb clk\n"); @@ -669,12 +669,6 @@ static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev) return dev_err_probe(phy->dev, PTR_ERR(phy->refclk), "failed to get ref clk\n"); - ret = clk_prepare_enable(phy->apbclk); - if (ret) { - dev_err(phy->dev, "failed to enable apbclk\n"); - return ret; - } - pm_runtime_get_noresume(phy->dev); pm_runtime_set_active(phy->dev); pm_runtime_enable(phy->dev); @@ -690,8 +684,6 @@ static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev) return 0; register_clk_failed: - clk_disable_unprepare(phy->apbclk); - return ret; } -- 2.51.0 From 2947c8065e9efdd3b6434d2817dc8896234a3fc0 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Wed, 5 Feb 2025 18:51:54 +0800 Subject: [PATCH 15/16] phy: phy-rockchip-samsung-hdptx: Swap the definitions of LCPLL_REF and ROPLL_REF According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097) to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0 selects the ROPLL. Signed-off-by: Damon Ding Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250205105157.580060-2-damon.ding@rock-chips.com Signed-off-by: Vinod Koul --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 35d5b762e5c4..dfcc37b1c8a6 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -94,8 +94,8 @@ #define LCPLL_ALONE_MODE BIT(1) /* CMN_REG(0097) */ #define DIG_CLK_SEL BIT(1) -#define ROPLL_REF BIT(1) -#define LCPLL_REF 0 +#define LCPLL_REF BIT(1) +#define ROPLL_REF 0 /* CMN_REG(0099) */ #define CMN_ROPLL_ALONE_MODE BIT(2) #define ROPLL_ALONE_MODE BIT(2) -- 2.51.0 From f706024107204cb0b640bac35ea47e7b91b8c71f Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Wed, 5 Feb 2025 18:51:55 +0800 Subject: [PATCH 16/16] phy: phy-rockchip-samsung-hdptx: Supplement some register names with their full version Complete the register names of CMN_REG(0081) and CMN_REG(0087) to their full version, and it can help to better match the datasheet. Signed-off-by: Damon Ding Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250205105157.580060-3-damon.ding@rock-chips.com Signed-off-by: Vinod Koul --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index dfcc37b1c8a6..77b817ac9059 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -82,14 +82,14 @@ #define ROPLL_SSC_EN BIT(0) /* CMN_REG(0081) */ #define OVRD_PLL_CD_CLK_EN BIT(8) -#define PLL_CD_HSCLK_EAST_EN BIT(0) +#define ANA_PLL_CD_HSCLK_EAST_EN BIT(0) /* CMN_REG(0086) */ #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4) #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1) #define PLL_PCG_CLK_EN BIT(0) /* CMN_REG(0087) */ -#define PLL_FRL_MODE_EN BIT(3) -#define PLL_TX_HS_CLK_EN BIT(2) +#define ANA_PLL_FRL_MODE_EN BIT(3) +#define ANA_PLL_TX_HS_CLK_EN BIT(2) /* CMN_REG(0089) */ #define LCPLL_ALONE_MODE BIT(1) /* CMN_REG(0097) */ -- 2.51.0