From fec450ca15af63649e219060f37a8ec673333726 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 8 Apr 2025 16:54:25 +0300 Subject: [PATCH 01/16] drm/display: hdmi: provide central data authority for ACR params HDMI standard defines recommended N and CTS values for Audio Clock Regeneration. Currently each driver implements those, frequently in somewhat unique way. Provide a generic helper for getting those values to be used by the HDMI drivers. The helper is added to drm_hdmi_helper.c rather than drm_hdmi_audio.c since HDMI drivers can be using this helper function even without switching to DRM HDMI Audio helpers. Note: currently this only handles the values per HDMI 1.4b Section 7.2 and HDMI 2.0 Section 9.2.1. Later the table can be expanded to accommodate for Deep Color TMDS char rates per HDMI 1.4 Appendix D and/or HDMI 2.0 / 2.1 Appendix C). Reviewed-by: Maxime Ripard Link: https://lore.kernel.org/r/20250408-drm-hdmi-acr-v2-1-dee7298ab1af@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/display/drm_hdmi_helper.c | 168 ++++++++++++++++++++++ include/drm/display/drm_hdmi_helper.h | 6 + 2 files changed, 174 insertions(+) diff --git a/drivers/gpu/drm/display/drm_hdmi_helper.c b/drivers/gpu/drm/display/drm_hdmi_helper.c index 74dd4d01dd9b..855cb02b827d 100644 --- a/drivers/gpu/drm/display/drm_hdmi_helper.c +++ b/drivers/gpu/drm/display/drm_hdmi_helper.c @@ -256,3 +256,171 @@ drm_hdmi_compute_mode_clock(const struct drm_display_mode *mode, return DIV_ROUND_CLOSEST_ULL(clock * bpc, 8); } EXPORT_SYMBOL(drm_hdmi_compute_mode_clock); + +struct drm_hdmi_acr_n_cts_entry { + unsigned int n; + unsigned int cts; +}; + +struct drm_hdmi_acr_data { + unsigned long tmds_clock_khz; + struct drm_hdmi_acr_n_cts_entry n_cts_32k, + n_cts_44k1, + n_cts_48k; +}; + +static const struct drm_hdmi_acr_data hdmi_acr_n_cts[] = { + { + /* "Other" entry */ + .n_cts_32k = { .n = 4096, }, + .n_cts_44k1 = { .n = 6272, }, + .n_cts_48k = { .n = 6144, }, + }, { + .tmds_clock_khz = 25175, + .n_cts_32k = { .n = 4576, .cts = 28125, }, + .n_cts_44k1 = { .n = 7007, .cts = 31250, }, + .n_cts_48k = { .n = 6864, .cts = 28125, }, + }, { + .tmds_clock_khz = 25200, + .n_cts_32k = { .n = 4096, .cts = 25200, }, + .n_cts_44k1 = { .n = 6272, .cts = 28000, }, + .n_cts_48k = { .n = 6144, .cts = 25200, }, + }, { + .tmds_clock_khz = 27000, + .n_cts_32k = { .n = 4096, .cts = 27000, }, + .n_cts_44k1 = { .n = 6272, .cts = 30000, }, + .n_cts_48k = { .n = 6144, .cts = 27000, }, + }, { + .tmds_clock_khz = 27027, + .n_cts_32k = { .n = 4096, .cts = 27027, }, + .n_cts_44k1 = { .n = 6272, .cts = 30030, }, + .n_cts_48k = { .n = 6144, .cts = 27027, }, + }, { + .tmds_clock_khz = 54000, + .n_cts_32k = { .n = 4096, .cts = 54000, }, + .n_cts_44k1 = { .n = 6272, .cts = 60000, }, + .n_cts_48k = { .n = 6144, .cts = 54000, }, + }, { + .tmds_clock_khz = 54054, + .n_cts_32k = { .n = 4096, .cts = 54054, }, + .n_cts_44k1 = { .n = 6272, .cts = 60060, }, + .n_cts_48k = { .n = 6144, .cts = 54054, }, + }, { + .tmds_clock_khz = 74176, + .n_cts_32k = { .n = 11648, .cts = 210937, }, /* and 210938 */ + .n_cts_44k1 = { .n = 17836, .cts = 234375, }, + .n_cts_48k = { .n = 11648, .cts = 140625, }, + }, { + .tmds_clock_khz = 74250, + .n_cts_32k = { .n = 4096, .cts = 74250, }, + .n_cts_44k1 = { .n = 6272, .cts = 82500, }, + .n_cts_48k = { .n = 6144, .cts = 74250, }, + }, { + .tmds_clock_khz = 148352, + .n_cts_32k = { .n = 11648, .cts = 421875, }, + .n_cts_44k1 = { .n = 8918, .cts = 234375, }, + .n_cts_48k = { .n = 5824, .cts = 140625, }, + }, { + .tmds_clock_khz = 148500, + .n_cts_32k = { .n = 4096, .cts = 148500, }, + .n_cts_44k1 = { .n = 6272, .cts = 165000, }, + .n_cts_48k = { .n = 6144, .cts = 148500, }, + }, { + .tmds_clock_khz = 296703, + .n_cts_32k = { .n = 5824, .cts = 421875, }, + .n_cts_44k1 = { .n = 4459, .cts = 234375, }, + .n_cts_48k = { .n = 5824, .cts = 281250, }, + }, { + .tmds_clock_khz = 297000, + .n_cts_32k = { .n = 3072, .cts = 222750, }, + .n_cts_44k1 = { .n = 4704, .cts = 247500, }, + .n_cts_48k = { .n = 5120, .cts = 247500, }, + }, { + .tmds_clock_khz = 593407, + .n_cts_32k = { .n = 5824, .cts = 843750, }, + .n_cts_44k1 = { .n = 8918, .cts = 937500, }, + .n_cts_48k = { .n = 5824, .cts = 562500, }, + }, { + .tmds_clock_khz = 594000, + .n_cts_32k = { .n = 3072, .cts = 445500, }, + .n_cts_44k1 = { .n = 9408, .cts = 990000, }, + .n_cts_48k = { .n = 6144, .cts = 594000, }, + }, +}; + +static int drm_hdmi_acr_find_tmds_entry(unsigned long tmds_clock_khz) +{ + int i; + + /* skip the "other" entry */ + for (i = 1; i < ARRAY_SIZE(hdmi_acr_n_cts); i++) { + if (hdmi_acr_n_cts[i].tmds_clock_khz == tmds_clock_khz) + return i; + } + + return 0; +} + +/** + * drm_hdmi_acr_get_n_cts() - get N and CTS values for Audio Clock Regeneration + * + * @tmds_char_rate: TMDS clock (char rate) as used by the HDMI connector + * @sample_rate: audio sample rate + * @out_n: a pointer to write the N value + * @out_cts: a pointer to write the CTS value + * + * Get the N and CTS values (either by calculating them or by returning data + * from the tables. This follows the HDMI 1.4b Section 7.2 "Audio Sample Clock + * Capture and Regeneration". + * + * Note, @sample_rate corresponds to the Fs value, see sections 7.2.4 - 7.2.6 + * on how to select Fs for non-L-PCM formats. + */ +void +drm_hdmi_acr_get_n_cts(unsigned long long tmds_char_rate, + unsigned int sample_rate, + unsigned int *out_n, + unsigned int *out_cts) +{ + /* be a bit more tolerant, especially for the 1.001 entries */ + unsigned long tmds_clock_khz = DIV_ROUND_CLOSEST_ULL(tmds_char_rate, 1000); + const struct drm_hdmi_acr_n_cts_entry *entry; + unsigned int n, cts, mult; + int tmds_idx; + + tmds_idx = drm_hdmi_acr_find_tmds_entry(tmds_clock_khz); + + /* + * Don't change the order, 192 kHz is divisible by 48k and 32k, but it + * should use 48k entry. + */ + if (sample_rate % 48000 == 0) { + entry = &hdmi_acr_n_cts[tmds_idx].n_cts_48k; + mult = sample_rate / 48000; + } else if (sample_rate % 44100 == 0) { + entry = &hdmi_acr_n_cts[tmds_idx].n_cts_44k1; + mult = sample_rate / 44100; + } else if (sample_rate % 32000 == 0) { + entry = &hdmi_acr_n_cts[tmds_idx].n_cts_32k; + mult = sample_rate / 32000; + } else { + entry = NULL; + } + + if (entry) { + n = entry->n * mult; + cts = entry->cts; + } else { + /* Recommended optimal value, HDMI 1.4b, Section 7.2.1 */ + n = 128 * sample_rate / 1000; + cts = 0; + } + + if (!cts) + cts = DIV_ROUND_CLOSEST_ULL(tmds_char_rate * n, + 128 * sample_rate); + + *out_n = n; + *out_cts = cts; +} +EXPORT_SYMBOL(drm_hdmi_acr_get_n_cts); diff --git a/include/drm/display/drm_hdmi_helper.h b/include/drm/display/drm_hdmi_helper.h index 57e3b18c15ec..09145c9ee9fc 100644 --- a/include/drm/display/drm_hdmi_helper.h +++ b/include/drm/display/drm_hdmi_helper.h @@ -28,4 +28,10 @@ unsigned long long drm_hdmi_compute_mode_clock(const struct drm_display_mode *mode, unsigned int bpc, enum hdmi_colorspace fmt); +void +drm_hdmi_acr_get_n_cts(unsigned long long tmds_char_rate, + unsigned int sample_rate, + unsigned int *out_n, + unsigned int *out_cts); + #endif -- 2.51.0 From 2c01d90998598b5f48b4ccdfdd3e7d407d094613 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:00 +0100 Subject: [PATCH 02/16] dt-bindings: gpu: img: Future-proofing enhancements The first compatible strings added for the AXE-1-16M are not sufficient to accurately describe all the IMG Rogue GPUs. The current "img,img-axe" string refers to the entire family of Series AXE GPUs, but this is primarily a marketing term and does not denote a level of hardware similarity any greater than just "Rogue". The more specific "img,img-axe-1-16m" string refers to individual AXE-1-16M GPU. For example, unlike the rest of the Series AXE GPUs, the AXE-1-16M only uses a single power domain. The situation is actually slightly worse than described in the first paragraph, since many "series" (such as Series BXS found in the TI AM68 among others and added later in this series) contain cores with both Rogue and Volcanic architectures. Besides attempting to move away from vague groupings defined only by marketing terms, we want to draw a line between properties inherent to the IP core and choices made by the silicon vendor at integration time. For instance, the number of power domains is a property of the IP core, whereas the decision to use one or multiple clocks is a vendor one. In the original compatible strings, we must use "ti,am62-gpu" to constrain both of these properties since the number of power domains cannot be fixed for "img,img-axe". Work is currently underway to add support for volcanic-based Imagination GPUs, for which bindings will be added in "img,powervr-volcanic.yaml". As alluded to previously, the split between rogue and volcanic cores is non-obvious at times, so add a generic top-level "img,img-rogue" compatible string here to allow for simpler differentiation in devicetrees without referring back to the bindings. The currently supported GPU (AXE-1-16M) only requires a single power domain. Subsequent patches will add support for BXS-4-64 MC1, which has two power domains. Add infrastructure now to allow for this. Also allow the dma-coherent property to be added to IMG Rogue GPUs, which are DMA devices. The decision for coherency is made at integration time and this property should be applied wherever it accurately describes the vendor integration. Note that the new required properties for power domains are conditional on the new base compatible string to avoid an ABI break. Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-1-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- .../bindings/gpu/img,powervr-rogue.yaml | 43 ++++++++++++++++--- 1 file changed, 38 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 256e252f8087..e1056bf2af84 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -12,10 +12,23 @@ maintainers: properties: compatible: - items: - - enum: - - ti,am62-gpu - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable + oneOf: + - items: + - enum: + - ti,am62-gpu + - const: img,img-axe-1-16m + # This deprecated element must be kept around to allow old kernels to + # work with newer dts. + - const: img,img-axe + - const: img,img-rogue + + # This legacy combination of compatible strings was introduced early on + # before the more specific GPU identifiers were used. + - items: + - enum: + - ti,am62-gpu + - const: img,img-axe + deprecated: true reg: maxItems: 1 @@ -37,6 +50,12 @@ properties: power-domains: maxItems: 1 + power-domain-names: + items: + - const: a + + dma-coherent: true + required: - compatible - reg @@ -47,6 +66,18 @@ required: additionalProperties: false allOf: + # Constraints added alongside the new compatible strings that would otherwise + # create an ABI break. + - if: + properties: + compatible: + contains: + const: img,img-rogue + then: + required: + - power-domains + - power-domain-names + - if: properties: compatible: @@ -64,10 +95,12 @@ examples: #include gpu@fd00000 { - compatible = "ti,am62-gpu", "img,img-axe"; + compatible = "ti,am62-gpu", "img,img-axe-1-16m", "img,img-axe", + "img,img-rogue"; reg = <0x0fd00000 0x20000>; clocks = <&k3_clks 187 0>; clock-names = "core"; interrupts = ; power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + power-domain-names = "a"; }; -- 2.51.0 From 86e3f3a694903bc77f6e80ed0de2c9384c5bb9be Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:01 +0100 Subject: [PATCH 03/16] dt-bindings: gpu: img: Add BXS-4-64 devicetree bindings Unlike AXE-1-16M, BXS-4-64 uses two power domains. Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock integration in the TI k3-j721s2. Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-2-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- .../bindings/gpu/img,powervr-rogue.yaml | 38 ++++++++++++++++++- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index e1056bf2af84..0fb2cd939aa4 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -21,6 +21,11 @@ properties: # work with newer dts. - const: img,img-axe - const: img,img-rogue + - items: + - enum: + - ti,j721s2-gpu + - const: img,img-bxs-4-64 + - const: img,img-rogue # This legacy combination of compatible strings was introduced early on # before the more specific GPU identifiers were used. @@ -48,11 +53,14 @@ properties: maxItems: 1 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 2 power-domain-names: items: - const: a + - const: b + minItems: 1 dma-coherent: true @@ -82,7 +90,33 @@ allOf: properties: compatible: contains: - const: ti,am62-gpu + const: img,img-axe-1-16m + then: + properties: + power-domains: + maxItems: 1 + power-domain-names: + maxItems: 1 + + - if: + properties: + compatible: + contains: + const: img,img-bxs-4-64 + then: + properties: + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - ti,am62-gpu + - ti,j721s2-gpu then: properties: clocks: -- 2.51.0 From 0fb32b777aecfb0fa09dcb3f05bd05acd9527b55 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Thu, 10 Apr 2025 10:55:02 +0100 Subject: [PATCH 04/16] drm/imagination: Update register defs for newer GPUs Update the register define header to a newer version that covers more recent GPUs, including BXS-4-64. Signed-off-by: Alessio Belle Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-3-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- .../gpu/drm/imagination/pvr_rogue_cr_defs.h | 153 +++++++++++++++--- 1 file changed, 134 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h index 2a90d02796d3..790c97f80a2a 100644 --- a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h +++ b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h @@ -827,6 +827,120 @@ #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_EN 0x00000001U +/* Register ROGUE_CR_EVENT_CLEAR */ +#define ROGUE_CR_EVENT_CLEAR 0x0138U +#define ROGUE_CR_EVENT_CLEAR__ROGUEXE__MASKFULL 0x00000000E01DFFFFULL +#define ROGUE_CR_EVENT_CLEAR__SIGNALS__MASKFULL 0x00000000E007FFFFULL +#define ROGUE_CR_EVENT_CLEAR_MASKFULL 0x00000000FFFFFFFFULL +#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_SHIFT 31U +#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_CLRMSK 0x7FFFFFFFU +#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_EN 0x80000000U +#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_SHIFT 30U +#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_CLRMSK 0xBFFFFFFFU +#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_EN 0x40000000U +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_SHIFT 29U +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_CLRMSK 0xDFFFFFFFU +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_EN 0x20000000U +#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_SHIFT 28U +#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_CLRMSK 0xEFFFFFFFU +#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_EN 0x10000000U +#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_SHIFT 27U +#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_CLRMSK 0xF7FFFFFFU +#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_EN 0x08000000U +#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_SHIFT 26U +#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_CLRMSK 0xFBFFFFFFU +#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_EN 0x04000000U +#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_SHIFT 25U +#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_CLRMSK 0xFDFFFFFFU +#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_EN 0x02000000U +#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_SHIFT 24U +#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_CLRMSK 0xFEFFFFFFU +#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_EN 0x01000000U +#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_SHIFT 23U +#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_CLRMSK 0xFF7FFFFFU +#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_EN 0x00800000U +#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_SHIFT 22U +#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_CLRMSK 0xFFBFFFFFU +#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_EN 0x00400000U +#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_SHIFT 21U +#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_CLRMSK 0xFFDFFFFFU +#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_EN 0x00200000U +#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_SHIFT 20U +#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_CLRMSK 0xFFEFFFFFU +#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_EN 0x00100000U +#define ROGUE_CR_EVENT_CLEAR_SAFETY_SHIFT 20U +#define ROGUE_CR_EVENT_CLEAR_SAFETY_CLRMSK 0xFFEFFFFFU +#define ROGUE_CR_EVENT_CLEAR_SAFETY_EN 0x00100000U +#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_SHIFT 19U +#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_CLRMSK 0xFFF7FFFFU +#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_EN 0x00080000U +#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_SHIFT 19U +#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_CLRMSK 0xFFF7FFFFU +#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_EN 0x00080000U +#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_SHIFT 18U +#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_CLRMSK 0xFFFBFFFFU +#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_EN 0x00040000U +#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_SHIFT 18U +#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_CLRMSK 0xFFFBFFFFU +#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_EN 0x00040000U +#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_SHIFT 17U +#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_CLRMSK 0xFFFDFFFFU +#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_EN 0x00020000U +#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_SHIFT 17U +#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_CLRMSK 0xFFFDFFFFU +#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_EN 0x00020000U +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_SHIFT 16U +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_CLRMSK 0xFFFEFFFFU +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_EN 0x00010000U +#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_SHIFT 15U +#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_CLRMSK 0xFFFF7FFFU +#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_EN 0x00008000U +#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_SHIFT 14U +#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_CLRMSK 0xFFFFBFFFU +#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_EN 0x00004000U +#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_SHIFT 13U +#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_CLRMSK 0xFFFFDFFFU +#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_EN 0x00002000U +#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_SHIFT 12U +#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_CLRMSK 0xFFFFEFFFU +#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_EN 0x00001000U +#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_SHIFT 11U +#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_CLRMSK 0xFFFFF7FFU +#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_EN 0x00000800U +#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_SHIFT 10U +#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_CLRMSK 0xFFFFFBFFU +#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_EN 0x00000400U +#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_SHIFT 9U +#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_CLRMSK 0xFFFFFDFFU +#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_EN 0x00000200U +#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_SHIFT 8U +#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_CLRMSK 0xFFFFFEFFU +#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_EN 0x00000100U +#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_SHIFT 7U +#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_CLRMSK 0xFFFFFF7FU +#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_EN 0x00000080U +#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_SHIFT 6U +#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_CLRMSK 0xFFFFFFBFU +#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_EN 0x00000040U +#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_SHIFT 5U +#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_CLRMSK 0xFFFFFFDFU +#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_EN 0x00000020U +#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_SHIFT 4U +#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_CLRMSK 0xFFFFFFEFU +#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_EN 0x00000010U +#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_SHIFT 3U +#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_CLRMSK 0xFFFFFFF7U +#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_EN 0x00000008U +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_SHIFT 2U +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_CLRMSK 0xFFFFFFFBU +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_EN 0x00000004U +#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_SHIFT 1U +#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_CLRMSK 0xFFFFFFFDU +#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_EN 0x00000002U +#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_SHIFT 0U +#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU +#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_EN 0x00000001U + /* Register ROGUE_CR_TIMER */ #define ROGUE_CR_TIMER 0x0160U #define ROGUE_CR_TIMER_MASKFULL 0x8000FFFFFFFFFFFFULL @@ -6031,25 +6145,6 @@ #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_SHIFT 0U #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U -/* Register ROGUE_CR_ECC_RAM_ERR_INJ */ -#define ROGUE_CR_ECC_RAM_ERR_INJ 0xF340U -#define ROGUE_CR_ECC_RAM_ERR_INJ_MASKFULL 0x000000000000001FULL -#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_SHIFT 4U -#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU -#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_EN 0x00000010U -#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_SHIFT 3U -#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_CLRMSK 0xFFFFFFF7U -#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_EN 0x00000008U -#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_SHIFT 2U -#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU -#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_EN 0x00000004U -#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_SHIFT 1U -#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_CLRMSK 0xFFFFFFFDU -#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_EN 0x00000002U -#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_SHIFT 0U -#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_CLRMSK 0xFFFFFFFEU -#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_EN 0x00000001U - /* Register ROGUE_CR_ECC_RAM_INIT_KICK */ #define ROGUE_CR_ECC_RAM_INIT_KICK 0xF348U #define ROGUE_CR_ECC_RAM_INIT_KICK_MASKFULL 0x000000000000001FULL @@ -6163,6 +6258,26 @@ #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U +/* Register ROGUE_CR_FAULT_FW_STATUS */ +#define ROGUE_CR_FAULT_FW_STATUS 0xF3B0U +#define ROGUE_CR_FAULT_FW_STATUS_MASKFULL 0x0000000000010001ULL +#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_SHIFT 16U +#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_CLRMSK 0xFFFEFFFFU +#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_EN 0x00010000U +#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_SHIFT 0U +#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_CLRMSK 0xFFFFFFFEU +#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_EN 0x00000001U + +/* Register ROGUE_CR_FAULT_FW_CLEAR */ +#define ROGUE_CR_FAULT_FW_CLEAR 0xF3B8U +#define ROGUE_CR_FAULT_FW_CLEAR_MASKFULL 0x0000000000010001ULL +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_SHIFT 16U +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_CLRMSK 0xFFFEFFFFU +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_EN 0x00010000U +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_SHIFT 0U +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_CLRMSK 0xFFFFFFFEU +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_EN 0x00000001U + /* Register ROGUE_CR_MTS_SAFETY_EVENT_ENABLE */ #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE 0xF3D8U #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL -- 2.51.0 From 2e8c6b27478c3acf411eb130ddd4817c518f2824 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:03 +0100 Subject: [PATCH 05/16] drm/imagination: Use new generic compatible string Follow-on from the companion dt-bindings change ("dt-bindings: gpu: img: More explicit compatible strings"), deprecating "img,img-axe" in favour of the more explicit combination of "img,img-rogue" and "img,img-axe-1-16m". Since all relevant details are interrogated from the device at runtime, we can match on the generic "img,img-rogue" and avoid adding more entries with NULL data members (barring hardware quirks). Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-4-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_drv.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagination/pvr_drv.c index 0639502137b4..3130193f8fff 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1473,6 +1473,13 @@ static void pvr_remove(struct platform_device *plat_dev) } static const struct of_device_id dt_match[] = { + { .compatible = "img,img-rogue", .data = NULL }, + + /* + * This legacy compatible string was introduced early on before the more generic + * "img,img-rogue" was added. Keep it around here for compatibility, but never use + * "img,img-axe" in new devicetrees. + */ { .compatible = "img,img-axe", .data = NULL }, {} }; -- 2.51.0 From 330e76d3169721a55658c3b4fed872df6b0d6239 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:04 +0100 Subject: [PATCH 06/16] drm/imagination: Add power domain control The first supported GPU only used a single power domain so this was automatically handled by the device runtime. In order to support multiple power domains, they must be enumerated from devicetree and linked to both the GPU device and each other to ensure correct power sequencing at start time. For all Imagination Rogue GPUs, power domains are named "a", "b", etc. and the sequence A->B->... is always valid for startup with the reverse true for shutdown. Note this is not always the *only* valid sequence, but it's simple and does not require special-casing for different GPU power topologies. Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-5-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_device.h | 8 ++ drivers/gpu/drm/imagination/pvr_drv.c | 7 ++ drivers/gpu/drm/imagination/pvr_power.c | 114 +++++++++++++++++++++++ drivers/gpu/drm/imagination/pvr_power.h | 3 + 4 files changed, 132 insertions(+) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h index 6d0dfacb677b..2dd8a8885fe0 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -131,6 +132,13 @@ struct pvr_device { */ struct clk *mem_clk; + struct pvr_device_power { + struct device **domain_devs; + struct device_link **domain_links; + + u32 domain_count; + } power; + /** @irq: IRQ number. */ int irq; diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagination/pvr_drv.c index 3130193f8fff..ac4f5855c569 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1411,6 +1411,10 @@ pvr_probe(struct platform_device *plat_dev) platform_set_drvdata(plat_dev, drm_dev); + err = pvr_power_domains_init(pvr_dev); + if (err) + return err; + init_rwsem(&pvr_dev->reset_sem); pvr_context_device_init(pvr_dev); @@ -1450,6 +1454,8 @@ err_watchdog_fini: err_context_fini: pvr_context_device_fini(pvr_dev); + pvr_power_domains_fini(pvr_dev); + return err; } @@ -1470,6 +1476,7 @@ static void pvr_remove(struct platform_device *plat_dev) pvr_watchdog_fini(pvr_dev); pvr_queue_device_fini(pvr_dev); pvr_context_device_fini(pvr_dev); + pvr_power_domains_fini(pvr_dev); } static const struct of_device_id dt_match[] = { diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imagination/pvr_power.c index ba7816fd28ec..19b079b357df 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -10,10 +10,13 @@ #include #include +#include #include #include #include +#include #include +#include #include #include #include @@ -431,3 +434,114 @@ pvr_watchdog_fini(struct pvr_device *pvr_dev) { cancel_delayed_work_sync(&pvr_dev->watchdog.work); } + +int pvr_power_domains_init(struct pvr_device *pvr_dev) +{ + struct device *dev = from_pvr_device(pvr_dev)->dev; + + struct device_link **domain_links __free(kfree) = NULL; + struct device **domain_devs __free(kfree) = NULL; + int domain_count; + int link_count; + + char dev_name[2] = "a"; + int err; + int i; + + domain_count = of_count_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells"); + if (domain_count < 0) + return domain_count; + + if (domain_count <= 1) + return 0; + + link_count = domain_count + (domain_count - 1); + + domain_devs = kcalloc(domain_count, sizeof(*domain_devs), GFP_KERNEL); + if (!domain_devs) + return -ENOMEM; + + domain_links = kcalloc(link_count, sizeof(*domain_links), GFP_KERNEL); + if (!domain_links) + return -ENOMEM; + + for (i = 0; i < domain_count; i++) { + struct device *domain_dev; + + dev_name[0] = 'a' + i; + domain_dev = dev_pm_domain_attach_by_name(dev, dev_name); + if (IS_ERR_OR_NULL(domain_dev)) { + err = domain_dev ? PTR_ERR(domain_dev) : -ENODEV; + goto err_detach; + } + + domain_devs[i] = domain_dev; + } + + for (i = 0; i < domain_count; i++) { + struct device_link *link; + + link = device_link_add(dev, domain_devs[i], DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); + if (!link) { + err = -ENODEV; + goto err_unlink; + } + + domain_links[i] = link; + } + + for (i = domain_count; i < link_count; i++) { + struct device_link *link; + + link = device_link_add(domain_devs[i - domain_count + 1], + domain_devs[i - domain_count], + DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); + if (!link) { + err = -ENODEV; + goto err_unlink; + } + + domain_links[i] = link; + } + + pvr_dev->power = (struct pvr_device_power){ + .domain_devs = no_free_ptr(domain_devs), + .domain_links = no_free_ptr(domain_links), + .domain_count = domain_count, + }; + + return 0; + +err_unlink: + while (--i >= 0) + device_link_del(domain_links[i]); + + i = domain_count; + +err_detach: + while (--i >= 0) + dev_pm_domain_detach(domain_devs[i], true); + + return err; +} + +void pvr_power_domains_fini(struct pvr_device *pvr_dev) +{ + const int domain_count = pvr_dev->power.domain_count; + + int i = domain_count + (domain_count - 1); + + while (--i >= 0) + device_link_del(pvr_dev->power.domain_links[i]); + + i = domain_count; + + while (--i >= 0) + dev_pm_domain_detach(pvr_dev->power.domain_devs[i], true); + + kfree(pvr_dev->power.domain_links); + kfree(pvr_dev->power.domain_devs); + + pvr_dev->power = (struct pvr_device_power){ 0 }; +} diff --git a/drivers/gpu/drm/imagination/pvr_power.h b/drivers/gpu/drm/imagination/pvr_power.h index 9a9312dcb2da..ada85674a7ca 100644 --- a/drivers/gpu/drm/imagination/pvr_power.h +++ b/drivers/gpu/drm/imagination/pvr_power.h @@ -38,4 +38,7 @@ pvr_power_put(struct pvr_device *pvr_dev) return pm_runtime_put(drm_dev->dev); } +int pvr_power_domains_init(struct pvr_device *pvr_dev); +void pvr_power_domains_fini(struct pvr_device *pvr_dev); + #endif /* PVR_POWER_H */ -- 2.51.0 From bdced61365b4eca917b6df37d3d47c2f7d096d87 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Thu, 10 Apr 2025 10:55:05 +0100 Subject: [PATCH 07/16] drm/imagination: Mask GPU IRQs in threaded handler Pass IRQF_ONESHOT flag to request_threaded_irq(), so that interrupts will be masked by the kernel until the end of the threaded IRQ handler. Since the calls to pvr_fw_irq_enable() and pvr_fw_irq_disable() are now redundant, remove them. Interrupts to the host from the soon-to-be-added RISC-V firmware processors cannot be masked in hardware. This change allows us to continue using the threaded handler in GPUs with a RISC-V firmware. For simplicity, the same approach is taken for all firmware processors. Signed-off-by: Alessio Belle Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-6-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_device.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/imagination/pvr_device.c index 1704c0268589..b6ce936f07c8 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -169,8 +169,6 @@ static irqreturn_t pvr_device_irq_thread_handler(int irq, void *data) ret = IRQ_HANDLED; } - /* Unmask FW irqs before returning, so new interrupts can be received. */ - pvr_fw_irq_enable(pvr_dev); return ret; } @@ -181,10 +179,6 @@ static irqreturn_t pvr_device_irq_handler(int irq, void *data) if (!pvr_fw_irq_pending(pvr_dev)) return IRQ_NONE; /* Spurious IRQ - ignore. */ - /* Mask the FW interrupts before waking up the thread. Will be unmasked - * when the thread handler is done processing events. - */ - pvr_fw_irq_disable(pvr_dev); return IRQ_WAKE_THREAD; } @@ -213,9 +207,13 @@ pvr_device_irq_init(struct pvr_device *pvr_dev) pvr_fw_irq_clear(pvr_dev); pvr_fw_irq_enable(pvr_dev); + /* + * The ONESHOT flag ensures IRQs are masked while the thread handler is + * running. + */ return request_threaded_irq(pvr_dev->irq, pvr_device_irq_handler, pvr_device_irq_thread_handler, - IRQF_SHARED, "gpu", pvr_dev); + IRQF_SHARED | IRQF_ONESHOT, "gpu", pvr_dev); } /** -- 2.51.0 From 96822d38ff574433e06a2ec0f88ebc50d44c8eaa Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Thu, 10 Apr 2025 10:55:06 +0100 Subject: [PATCH 08/16] drm/imagination: Handle Rogue safety event IRQs Extend interrupt handling logic to check for safety event IRQs, then clear and handle them in the IRQ handler thread. Safety events need to be checked and cleared with a different set of GPU registers than those the IRQ handler has been using so far. Only two safety events need to be handled on the host: FW fault (ECC error correction or detection) and device watchdog timeout. Handling right now simply consists of clearing any error and logging the event. If either of these events results in an unrecoverable GPU or FW, the driver will eventually attempt to recover from it e.g. via pvr_power_reset(). Note that Rogue GPUs may send interrupts to the host for all types of safety events, not just the two above. For events not handled by the host, clearing the associated interrupt is sufficient. Signed-off-by: Alessio Belle Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-7-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_device.c | 113 ++++++++++++++++++++++- drivers/gpu/drm/imagination/pvr_device.h | 3 + drivers/gpu/drm/imagination/pvr_fw.c | 3 + 3 files changed, 117 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/imagination/pvr_device.c index b6ce936f07c8..a47dd1dd8243 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -146,9 +146,61 @@ static void pvr_device_process_active_queues(struct pvr_device *pvr_dev) mutex_unlock(&pvr_dev->queues.lock); } +static bool pvr_device_safety_irq_pending(struct pvr_device *pvr_dev) +{ + u32 events; + + WARN_ON_ONCE(!pvr_dev->has_safety_events); + + events = pvr_cr_read32(pvr_dev, ROGUE_CR_EVENT_STATUS); + + return (events & ROGUE_CR_EVENT_STATUS_SAFETY_EN) != 0; +} + +static void pvr_device_safety_irq_clear(struct pvr_device *pvr_dev) +{ + WARN_ON_ONCE(!pvr_dev->has_safety_events); + + pvr_cr_write32(pvr_dev, ROGUE_CR_EVENT_CLEAR, + ROGUE_CR_EVENT_CLEAR_SAFETY_EN); +} + +static void pvr_device_handle_safety_events(struct pvr_device *pvr_dev) +{ + struct drm_device *drm_dev = from_pvr_device(pvr_dev); + u32 events; + + WARN_ON_ONCE(!pvr_dev->has_safety_events); + + events = pvr_cr_read32(pvr_dev, ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE); + + /* Handle only these events on the host and leave the rest to the FW. */ + events &= ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_EN | + ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_EN; + + pvr_cr_write32(pvr_dev, ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE, events); + + if (events & ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_EN) { + u32 fault_fw = pvr_cr_read32(pvr_dev, ROGUE_CR_FAULT_FW_STATUS); + + pvr_cr_write32(pvr_dev, ROGUE_CR_FAULT_FW_CLEAR, fault_fw); + + drm_info(drm_dev, "Safety event: FW fault (mask=0x%08x)\n", fault_fw); + } + + if (events & ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_EN) { + /* + * The watchdog timer is disabled by the driver so this event + * should never be fired. + */ + drm_info(drm_dev, "Safety event: Watchdog timeout\n"); + } +} + static irqreturn_t pvr_device_irq_thread_handler(int irq, void *data) { struct pvr_device *pvr_dev = data; + struct drm_device *drm_dev = from_pvr_device(pvr_dev); irqreturn_t ret = IRQ_NONE; /* We are in the threaded handler, we can keep dequeuing events until we @@ -164,24 +216,76 @@ static irqreturn_t pvr_device_irq_thread_handler(int irq, void *data) pvr_device_process_active_queues(pvr_dev); } - pm_runtime_mark_last_busy(from_pvr_device(pvr_dev)->dev); + pm_runtime_mark_last_busy(drm_dev->dev); ret = IRQ_HANDLED; } + if (pvr_dev->has_safety_events) { + int err; + + /* + * Ensure the GPU is powered on since some safety events (such + * as ECC faults) can happen outside of job submissions, which + * are otherwise the only time a power reference is held. + */ + err = pvr_power_get(pvr_dev); + if (err) { + drm_err_ratelimited(drm_dev, + "%s: could not take power reference (%d)\n", + __func__, err); + return ret; + } + + while (pvr_device_safety_irq_pending(pvr_dev)) { + pvr_device_safety_irq_clear(pvr_dev); + pvr_device_handle_safety_events(pvr_dev); + + ret = IRQ_HANDLED; + } + + pvr_power_put(pvr_dev); + } + return ret; } static irqreturn_t pvr_device_irq_handler(int irq, void *data) { struct pvr_device *pvr_dev = data; + bool safety_irq_pending = false; + + if (pvr_dev->has_safety_events) + safety_irq_pending = pvr_device_safety_irq_pending(pvr_dev); - if (!pvr_fw_irq_pending(pvr_dev)) + if (!pvr_fw_irq_pending(pvr_dev) && !safety_irq_pending) return IRQ_NONE; /* Spurious IRQ - ignore. */ return IRQ_WAKE_THREAD; } +static void pvr_device_safety_irq_init(struct pvr_device *pvr_dev) +{ + u32 num_ecc_rams = 0; + + /* + * Safety events are an optional feature of the RogueXE platform. They + * are only enabled if at least one of ECC memory or the watchdog timer + * are present in HW. While safety events can be generated by other + * systems, that will never happen if the above mentioned hardware is + * not present. + */ + if (!PVR_HAS_FEATURE(pvr_dev, roguexe)) { + pvr_dev->has_safety_events = false; + return; + } + + PVR_FEATURE_VALUE(pvr_dev, ecc_rams, &num_ecc_rams); + + pvr_dev->has_safety_events = + num_ecc_rams > 0 || PVR_HAS_FEATURE(pvr_dev, watchdog_timer); +} + /** * pvr_device_irq_init() - Initialise IRQ required by a PowerVR device * @pvr_dev: Target PowerVR device. @@ -199,6 +303,8 @@ pvr_device_irq_init(struct pvr_device *pvr_dev) init_waitqueue_head(&pvr_dev->kccb.rtn_q); + pvr_device_safety_irq_init(pvr_dev); + pvr_dev->irq = platform_get_irq(plat_dev, 0); if (pvr_dev->irq < 0) return pvr_dev->irq; @@ -207,6 +313,9 @@ pvr_device_irq_init(struct pvr_device *pvr_dev) pvr_fw_irq_clear(pvr_dev); pvr_fw_irq_enable(pvr_dev); + if (pvr_dev->has_safety_events) + pvr_device_safety_irq_clear(pvr_dev); + /* * The ONESHOT flag ensures IRQs are masked while the thread handler is * running. diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h index 2dd8a8885fe0..6c01d96657de 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -308,6 +308,9 @@ struct pvr_device { * struct pvr_file. */ spinlock_t ctx_list_lock; + + /** @has_safety_events: Whether this device can raise safety events. */ + bool has_safety_events; }; /** diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagination/pvr_fw.c index 012596402a33..17c29b5081f4 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -437,6 +437,9 @@ fw_runtime_cfg_init(void *cpu_ptr, void *priv) runtime_cfg->active_pm_latency_persistant = true; WARN_ON(PVR_FEATURE_VALUE(pvr_dev, num_clusters, &runtime_cfg->default_dusts_num_init) != 0); + + /* Keep watchdog timer disabled. */ + runtime_cfg->wdg_period_us = 0; } static void -- 2.51.0 From 2c08b72598cc15eafbf5c9c3870e5c29e21f4827 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:07 +0100 Subject: [PATCH 09/16] drm/imagination: Remove firmware enable_reg After a previous commit ("drm/imagination: Mask GPU IRQs in threaded handler"), this register is now only used to enable firmware interrupts at start-of-day. This is, however, unnecessary since they are enabled by default. In addition, the soon-to-be-added RISC-V firmware processors do not have an equivalent register. Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-8-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_device.c | 1 - drivers/gpu/drm/imagination/pvr_fw.h | 11 +---------- drivers/gpu/drm/imagination/pvr_fw_meta.c | 1 - drivers/gpu/drm/imagination/pvr_fw_mips.c | 1 - 4 files changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/imagination/pvr_device.c index a47dd1dd8243..1e488a30c784 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -311,7 +311,6 @@ pvr_device_irq_init(struct pvr_device *pvr_dev) /* Clear any pending events before requesting the IRQ line. */ pvr_fw_irq_clear(pvr_dev); - pvr_fw_irq_enable(pvr_dev); if (pvr_dev->has_safety_events) pvr_device_safety_irq_clear(pvr_dev); diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h index b7966bd574a9..29bae4bc244a 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -188,9 +188,6 @@ struct pvr_fw_defs { * processor backend in pvr_fw_funcs::init(). */ struct { - /** @enable_reg: FW interrupt enable register. */ - u32 enable_reg; - /** @status_reg: FW interrupt status register. */ u32 status_reg; @@ -202,7 +199,7 @@ struct pvr_fw_defs { */ u32 clear_reg; - /** @event_mask: Bitmask of events to listen for. */ + /** @event_mask: Bitmask of events to listen for in the status_reg. */ u32 event_mask; /** @clear_mask: Value to write to the clear_reg in order to clear FW IRQs. */ @@ -412,12 +409,6 @@ struct pvr_fw_device { #define pvr_fw_irq_clear(pvr_dev) \ pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_mask) -#define pvr_fw_irq_enable(pvr_dev) \ - pvr_fw_irq_write_reg(pvr_dev, enable, (pvr_dev)->fw_dev.defs->irq.event_mask) - -#define pvr_fw_irq_disable(pvr_dev) \ - pvr_fw_irq_write_reg(pvr_dev, enable, 0) - extern const struct pvr_fw_defs pvr_fw_defs_meta; extern const struct pvr_fw_defs pvr_fw_defs_mips; diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c index c7cfdd60116d..77596a2a6c4e 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -547,7 +547,6 @@ const struct pvr_fw_defs pvr_fw_defs_meta = { .wrapper_init = pvr_meta_wrapper_init, .has_fixed_data_addr = pvr_meta_has_fixed_data_addr, .irq = { - .enable_reg = ROGUE_CR_META_SP_MSLVIRQENABLE, .status_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, .clear_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, .event_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/imagination/pvr_fw_mips.c index ee0735b745a9..c73902bcf8e4 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -241,7 +241,6 @@ const struct pvr_fw_defs pvr_fw_defs_mips = { .wrapper_init = pvr_mips_wrapper_init, .has_fixed_data_addr = pvr_mips_has_fixed_data_addr, .irq = { - .enable_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE, .status_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, .clear_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, .event_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, -- 2.51.0 From 091ffb00b5eca4a872244bc8ce412e7675e9cafe Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:08 +0100 Subject: [PATCH 10/16] drm/imagination: Rename event_mask -> status_mask Now that enable_reg isn't used, rename the previously shared event_mask to status_mask since it's only used with status_reg. Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-9-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_fw.h | 6 +++--- drivers/gpu/drm/imagination/pvr_fw_meta.c | 2 +- drivers/gpu/drm/imagination/pvr_fw_mips.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h index 29bae4bc244a..eead74483572 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -199,8 +199,8 @@ struct pvr_fw_defs { */ u32 clear_reg; - /** @event_mask: Bitmask of events to listen for in the status_reg. */ - u32 event_mask; + /** @status_mask: Bitmask of events to listen for in the status_reg. */ + u32 status_mask; /** @clear_mask: Value to write to the clear_reg in order to clear FW IRQs. */ u32 clear_mask; @@ -404,7 +404,7 @@ struct pvr_fw_device { pvr_cr_write32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg, value) #define pvr_fw_irq_pending(pvr_dev) \ - (pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.event_mask) + (pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.status_mask) #define pvr_fw_irq_clear(pvr_dev) \ pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_mask) diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c index 77596a2a6c4e..892823826bf2 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -549,7 +549,7 @@ const struct pvr_fw_defs pvr_fw_defs_meta = { .irq = { .status_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, .clear_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, - .event_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, + .status_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, .clear_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, }, }; diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/imagination/pvr_fw_mips.c index c73902bcf8e4..567251a663de 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -243,7 +243,7 @@ const struct pvr_fw_defs pvr_fw_defs_mips = { .irq = { .status_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, .clear_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, - .event_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, + .status_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, .clear_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN, }, }; -- 2.51.0 From 28dbcfbc01f32ac9c7c5c5f7b3a12c8cf701a989 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:09 +0100 Subject: [PATCH 11/16] drm/imagination: Make has_fixed_data_addr a value This is currently a callback function which takes no parameters; there's no reason for this so let's make it a straightforward value in pvr_fw_defs. Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-10-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_fw.c | 2 +- drivers/gpu/drm/imagination/pvr_fw.h | 23 ++++++++--------------- drivers/gpu/drm/imagination/pvr_fw_meta.c | 8 +------- drivers/gpu/drm/imagination/pvr_fw_mips.c | 8 +------- 4 files changed, 11 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagination/pvr_fw.c index 17c29b5081f4..3441c378d91c 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -662,7 +662,7 @@ pvr_fw_process(struct pvr_device *pvr_dev) return PTR_ERR(fw_code_ptr); } - if (pvr_dev->fw_dev.defs->has_fixed_data_addr()) { + if (pvr_dev->fw_dev.defs->has_fixed_data_addr) { u32 base_addr = private_data->base_addr & pvr_dev->fw_dev.fw_heap_info.offset_mask; fw_data_ptr = diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h index eead74483572..180d310074e3 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -166,21 +166,6 @@ struct pvr_fw_defs { */ int (*wrapper_init)(struct pvr_device *pvr_dev); - /** - * @has_fixed_data_addr: - * - * Called to check if firmware fixed data must be loaded at the address given by the - * firmware layout table. - * - * This function is mandatory. - * - * Returns: - * * %true if firmware fixed data must be loaded at the address given by the firmware - * layout table. - * * %false otherwise. - */ - bool (*has_fixed_data_addr)(void); - /** * @irq: FW Interrupt information. * @@ -205,6 +190,14 @@ struct pvr_fw_defs { /** @clear_mask: Value to write to the clear_reg in order to clear FW IRQs. */ u32 clear_mask; } irq; + + /** + * @has_fixed_data_addr: Specify whether the firmware fixed data must be loaded at the + * address given by the firmware layout table. + * + * This value is mandatory. + */ + bool has_fixed_data_addr; }; /** diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c index 892823826bf2..41485769fc7c 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -532,12 +532,6 @@ pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj) fw_obj->fw_mm_node.start, fw_obj->fw_mm_node.size); } -static bool -pvr_meta_has_fixed_data_addr(void) -{ - return false; -} - const struct pvr_fw_defs pvr_fw_defs_meta = { .init = pvr_meta_init, .fw_process = pvr_meta_fw_process, @@ -545,11 +539,11 @@ const struct pvr_fw_defs pvr_fw_defs_meta = { .vm_unmap = pvr_meta_vm_unmap, .get_fw_addr_with_offset = pvr_meta_get_fw_addr_with_offset, .wrapper_init = pvr_meta_wrapper_init, - .has_fixed_data_addr = pvr_meta_has_fixed_data_addr, .irq = { .status_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, .clear_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, .status_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, .clear_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, }, + .has_fixed_data_addr = false, }; diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/imagination/pvr_fw_mips.c index 567251a663de..5feae0dc85ab 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -225,12 +225,6 @@ pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset) ROGUE_FW_HEAP_MIPS_BASE; } -static bool -pvr_mips_has_fixed_data_addr(void) -{ - return true; -} - const struct pvr_fw_defs pvr_fw_defs_mips = { .init = pvr_mips_init, .fini = pvr_mips_fini, @@ -239,11 +233,11 @@ const struct pvr_fw_defs pvr_fw_defs_mips = { .vm_unmap = pvr_vm_mips_unmap, .get_fw_addr_with_offset = pvr_mips_get_fw_addr_with_offset, .wrapper_init = pvr_mips_wrapper_init, - .has_fixed_data_addr = pvr_mips_has_fixed_data_addr, .irq = { .status_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, .clear_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, .status_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, .clear_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN, }, + .has_fixed_data_addr = true, }; -- 2.51.0 From 544b9b3b6fbd28473df9be42c815b2a5d97ae37b Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:10 +0100 Subject: [PATCH 12/16] drm/imagination: Use a lookup table for fw defs With more than two firmware processor types, the if/else chain in pvr_fw_init() gets a bit ridiculous. Use a static array indexed on pvr_fw_processor_type (which is now a proper enum instead of #defines) instead. Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-11-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_device.h | 4 ---- drivers/gpu/drm/imagination/pvr_fw.c | 21 ++++++++++++++++----- drivers/gpu/drm/imagination/pvr_fw.h | 7 +++++++ 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h index 6c01d96657de..12bf0b9e5bfb 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -739,8 +739,4 @@ pvr_ioctl_union_padding_check(void *instance, size_t union_offset, __union_size, __member_size); \ }) -#define PVR_FW_PROCESSOR_TYPE_META 0 -#define PVR_FW_PROCESSOR_TYPE_MIPS 1 -#define PVR_FW_PROCESSOR_TYPE_RISCV 2 - #endif /* PVR_DEVICE_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagination/pvr_fw.c index 3441c378d91c..962b8cb2119e 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -938,16 +938,27 @@ pvr_fw_validate_init_device_info(struct pvr_device *pvr_dev) int pvr_fw_init(struct pvr_device *pvr_dev) { + static const struct pvr_fw_defs *fw_defs[PVR_FW_PROCESSOR_TYPE_COUNT] = { + [PVR_FW_PROCESSOR_TYPE_META] = &pvr_fw_defs_meta, + [PVR_FW_PROCESSOR_TYPE_MIPS] = &pvr_fw_defs_mips, + [PVR_FW_PROCESSOR_TYPE_RISCV] = NULL, + }; + u32 kccb_size_log2 = ROGUE_FWIF_KCCB_NUMCMDS_LOG2_DEFAULT; u32 kccb_rtn_size = (1 << kccb_size_log2) * sizeof(*pvr_dev->kccb.rtn); struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev; int err; - if (fw_dev->processor_type == PVR_FW_PROCESSOR_TYPE_META) - fw_dev->defs = &pvr_fw_defs_meta; - else if (fw_dev->processor_type == PVR_FW_PROCESSOR_TYPE_MIPS) - fw_dev->defs = &pvr_fw_defs_mips; - else + if (fw_dev->processor_type >= PVR_FW_PROCESSOR_TYPE_COUNT) + return -EINVAL; + + fw_dev->defs = fw_defs[fw_dev->processor_type]; + + /* + * Not all firmware processor types are currently supported. + * Once they are, this check can be removed. + */ + if (!fw_dev->defs) return -EINVAL; err = fw_dev->defs->init(pvr_dev); diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h index 180d310074e3..88ad713468ce 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -402,6 +402,13 @@ struct pvr_fw_device { #define pvr_fw_irq_clear(pvr_dev) \ pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_mask) +enum pvr_fw_processor_type { + PVR_FW_PROCESSOR_TYPE_META = 0, + PVR_FW_PROCESSOR_TYPE_MIPS, + PVR_FW_PROCESSOR_TYPE_RISCV, + PVR_FW_PROCESSOR_TYPE_COUNT, +}; + extern const struct pvr_fw_defs pvr_fw_defs_meta; extern const struct pvr_fw_defs pvr_fw_defs_mips; -- 2.51.0 From 89b3c4a5cc1b95f09f5fa5c183aa9d7a65309eac Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:11 +0100 Subject: [PATCH 13/16] drm/imagination: Use callbacks for fw irq handling This allows for more versatility in checking and clearing firmware registers used for interrupt handling. Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-12-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_device.h | 18 +++++++++ drivers/gpu/drm/imagination/pvr_fw.h | 45 +++++++---------------- drivers/gpu/drm/imagination/pvr_fw_meta.c | 22 ++++++++--- drivers/gpu/drm/imagination/pvr_fw_mips.c | 22 ++++++++--- 4 files changed, 63 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h index 12bf0b9e5bfb..eb5da8c7040f 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -739,4 +739,22 @@ pvr_ioctl_union_padding_check(void *instance, size_t union_offset, __union_size, __member_size); \ }) +/* + * These utility functions should more properly be placed in pvr_fw.h, but that + * would cause a dependency cycle between that header and this one. Since + * they're primarily used in pvr_device.c, let's put them in here for now. + */ + +static __always_inline bool +pvr_fw_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_dev->fw_dev.defs->irq_pending(pvr_dev); +} + +static __always_inline void +pvr_fw_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_dev->fw_dev.defs->irq_clear(pvr_dev); +} + #endif /* PVR_DEVICE_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h index 88ad713468ce..ab69f40a7fbc 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -167,29 +167,22 @@ struct pvr_fw_defs { int (*wrapper_init)(struct pvr_device *pvr_dev); /** - * @irq: FW Interrupt information. + * @irq_pending: Check interrupt status register for pending interrupts. * - * Those are processor dependent, and should be initialized by the - * processor backend in pvr_fw_funcs::init(). + * @pvr_dev: Target PowerVR device. + * + * This function is mandatory. */ - struct { - /** @status_reg: FW interrupt status register. */ - u32 status_reg; + bool (*irq_pending)(struct pvr_device *pvr_dev); - /** - * @clear_reg: FW interrupt clear register. - * - * If @status_reg == @clear_reg, we clear by write a bit to zero, - * otherwise we clear by writing a bit to one. - */ - u32 clear_reg; - - /** @status_mask: Bitmask of events to listen for in the status_reg. */ - u32 status_mask; - - /** @clear_mask: Value to write to the clear_reg in order to clear FW IRQs. */ - u32 clear_mask; - } irq; + /** + * @irq_clear: Clear pending interrupts. + * + * @pvr_dev: Target PowerVR device. + * + * This function is mandatory. + */ + void (*irq_clear)(struct pvr_device *pvr_dev); /** * @has_fixed_data_addr: Specify whether the firmware fixed data must be loaded at the @@ -390,18 +383,6 @@ struct pvr_fw_device { } fw_objs; }; -#define pvr_fw_irq_read_reg(pvr_dev, name) \ - pvr_cr_read32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg) - -#define pvr_fw_irq_write_reg(pvr_dev, name, value) \ - pvr_cr_write32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg, value) - -#define pvr_fw_irq_pending(pvr_dev) \ - (pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.status_mask) - -#define pvr_fw_irq_clear(pvr_dev) \ - pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_mask) - enum pvr_fw_processor_type { PVR_FW_PROCESSOR_TYPE_META = 0, PVR_FW_PROCESSOR_TYPE_MIPS, diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c index 41485769fc7c..60db3668ad3c 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -532,6 +532,20 @@ pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj) fw_obj->fw_mm_node.start, fw_obj->fw_mm_node.size); } +static bool +pvr_meta_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS) & + ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN; +} + +static void +pvr_meta_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS, + ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK); +} + const struct pvr_fw_defs pvr_fw_defs_meta = { .init = pvr_meta_init, .fw_process = pvr_meta_fw_process, @@ -539,11 +553,7 @@ const struct pvr_fw_defs pvr_fw_defs_meta = { .vm_unmap = pvr_meta_vm_unmap, .get_fw_addr_with_offset = pvr_meta_get_fw_addr_with_offset, .wrapper_init = pvr_meta_wrapper_init, - .irq = { - .status_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, - .clear_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, - .status_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, - .clear_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, - }, + .irq_pending = pvr_meta_irq_pending, + .irq_clear = pvr_meta_irq_clear, .has_fixed_data_addr = false, }; diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/imagination/pvr_fw_mips.c index 5feae0dc85ab..7526dddbf520 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -225,6 +225,20 @@ pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset) ROGUE_FW_HEAP_MIPS_BASE; } +static bool +pvr_mips_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS) & + ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN; +} + +static void +pvr_mips_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, + ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN); +} + const struct pvr_fw_defs pvr_fw_defs_mips = { .init = pvr_mips_init, .fini = pvr_mips_fini, @@ -233,11 +247,7 @@ const struct pvr_fw_defs pvr_fw_defs_mips = { .vm_unmap = pvr_vm_mips_unmap, .get_fw_addr_with_offset = pvr_mips_get_fw_addr_with_offset, .wrapper_init = pvr_mips_wrapper_init, - .irq = { - .status_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, - .clear_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, - .status_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, - .clear_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN, - }, + .irq_pending = pvr_mips_irq_pending, + .irq_clear = pvr_mips_irq_clear, .has_fixed_data_addr = true, }; -- 2.51.0 From f48485ab506850b4e35ff56550568f710a22a586 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:12 +0100 Subject: [PATCH 14/16] drm/imagination: Move ELF fw utils to common file Currently only MIPS firmware processors use ELF-formatted firmware. When adding support for RISC-V firmware processors, it will be useful to have ELF handling functions ready to go. Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-13-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/Makefile | 1 + drivers/gpu/drm/imagination/pvr_fw.h | 5 ++ drivers/gpu/drm/imagination/pvr_fw_mips.c | 58 +------------------- drivers/gpu/drm/imagination/pvr_fw_util.c | 66 +++++++++++++++++++++++ 4 files changed, 74 insertions(+), 56 deletions(-) create mode 100644 drivers/gpu/drm/imagination/pvr_fw_util.c diff --git a/drivers/gpu/drm/imagination/Makefile b/drivers/gpu/drm/imagination/Makefile index 3d9d4d40fb80..f45782063f43 100644 --- a/drivers/gpu/drm/imagination/Makefile +++ b/drivers/gpu/drm/imagination/Makefile @@ -14,6 +14,7 @@ powervr-y := \ pvr_fw_mips.o \ pvr_fw_startstop.o \ pvr_fw_trace.o \ + pvr_fw_util.o \ pvr_gem.o \ pvr_hwrt.o \ pvr_job.o \ diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h index ab69f40a7fbc..e120eae06bf7 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -478,4 +478,9 @@ pvr_fw_object_get_fw_addr(struct pvr_fw_object *fw_obj, u32 *fw_addr_out) pvr_fw_object_get_fw_addr_offset(fw_obj, 0, fw_addr_out); } +/* Util functions defined in pvr_fw_util.c. These are intended for use in pvr_fw_.c files. */ +int +pvr_fw_process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code_ptr, + u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr); + #endif /* PVR_FW_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/imagination/pvr_fw_mips.c index 7526dddbf520..6914fc46db50 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -8,7 +8,6 @@ #include "pvr_rogue_mips.h" #include "pvr_vm_mips.h" -#include #include #include @@ -16,59 +15,6 @@ #define ROGUE_FW_HEAP_MIPS_SHIFT 24 /* 16 MB */ #define ROGUE_FW_HEAP_MIPS_RESERVED_SIZE SZ_1M -/** - * process_elf_command_stream() - Process ELF firmware image and populate - * firmware sections - * @pvr_dev: Device pointer. - * @fw: Pointer to firmware image. - * @fw_code_ptr: Pointer to FW code section. - * @fw_data_ptr: Pointer to FW data section. - * @fw_core_code_ptr: Pointer to FW coremem code section. - * @fw_core_data_ptr: Pointer to FW coremem data section. - * - * Returns : - * * 0 on success, or - * * -EINVAL on any error in ELF command stream. - */ -static int -process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code_ptr, - u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr) -{ - struct elf32_hdr *header = (struct elf32_hdr *)fw; - struct elf32_phdr *program_header = (struct elf32_phdr *)(fw + header->e_phoff); - struct drm_device *drm_dev = from_pvr_device(pvr_dev); - int err; - - for (u32 entry = 0; entry < header->e_phnum; entry++, program_header++) { - void *write_addr; - - /* Only consider loadable entries in the ELF segment table */ - if (program_header->p_type != PT_LOAD) - continue; - - err = pvr_fw_find_mmu_segment(pvr_dev, program_header->p_vaddr, - program_header->p_memsz, fw_code_ptr, fw_data_ptr, - fw_core_code_ptr, fw_core_data_ptr, &write_addr); - if (err) { - drm_err(drm_dev, - "Addr 0x%x (size: %d) not found in any firmware segment", - program_header->p_vaddr, program_header->p_memsz); - return err; - } - - /* Write to FW allocation only if available */ - if (write_addr) { - memcpy(write_addr, fw + program_header->p_offset, - program_header->p_filesz); - - memset((u8 *)write_addr + program_header->p_filesz, 0, - program_header->p_memsz - program_header->p_filesz); - } - } - - return 0; -} - static int pvr_mips_init(struct pvr_device *pvr_dev) { @@ -98,8 +44,8 @@ pvr_mips_fw_process(struct pvr_device *pvr_dev, const u8 *fw, dma_addr_t dma_addr; int err; - err = process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr, fw_core_code_ptr, - fw_core_data_ptr); + err = pvr_fw_process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr, + fw_core_code_ptr, fw_core_data_ptr); if (err) return err; diff --git a/drivers/gpu/drm/imagination/pvr_fw_util.c b/drivers/gpu/drm/imagination/pvr_fw_util.c new file mode 100644 index 000000000000..377fe72d86b8 --- /dev/null +++ b/drivers/gpu/drm/imagination/pvr_fw_util.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* Copyright (c) 2024 Imagination Technologies Ltd. */ + +#include "pvr_device.h" +#include "pvr_fw.h" + +#include +#include + +#include +#include +#include + +/** + * pvr_fw_process_elf_command_stream() - Process ELF firmware image and populate + * firmware sections + * @pvr_dev: Device pointer. + * @fw: Pointer to firmware image. + * @fw_code_ptr: Pointer to FW code section. + * @fw_data_ptr: Pointer to FW data section. + * @fw_core_code_ptr: Pointer to FW coremem code section. + * @fw_core_data_ptr: Pointer to FW coremem data section. + * + * Returns : + * * 0 on success, or + * * -EINVAL on any error in ELF command stream. + */ +int +pvr_fw_process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw, + u8 *fw_code_ptr, u8 *fw_data_ptr, + u8 *fw_core_code_ptr, u8 *fw_core_data_ptr) +{ + struct elf32_hdr *header = (struct elf32_hdr *)fw; + struct elf32_phdr *program_header = (struct elf32_phdr *)(fw + header->e_phoff); + struct drm_device *drm_dev = from_pvr_device(pvr_dev); + int err; + + for (u32 entry = 0; entry < header->e_phnum; entry++, program_header++) { + void *write_addr; + + /* Only consider loadable entries in the ELF segment table */ + if (program_header->p_type != PT_LOAD) + continue; + + err = pvr_fw_find_mmu_segment(pvr_dev, program_header->p_vaddr, + program_header->p_memsz, fw_code_ptr, fw_data_ptr, + fw_core_code_ptr, fw_core_data_ptr, &write_addr); + if (err) { + drm_err(drm_dev, + "Addr 0x%x (size: %d) not found in any firmware segment", + program_header->p_vaddr, program_header->p_memsz); + return err; + } + + /* Write to FW allocation only if available */ + if (write_addr) { + memcpy(write_addr, fw + program_header->p_offset, + program_header->p_filesz); + + memset((u8 *)write_addr + program_header->p_filesz, 0, + program_header->p_memsz - program_header->p_filesz); + } + } + + return 0; +} -- 2.51.0 From 171f378d2a23db92d3443173f5fd7f25633ec39d Mon Sep 17 00:00:00 2001 From: Sarah Walker Date: Thu, 10 Apr 2025 10:55:13 +0100 Subject: [PATCH 15/16] drm/imagination: Add RISC-V firmware processor support Newer PowerVR GPUs (such as the BXS-4-64 MC1) use a RISC-V firmware processor instead of the previous MIPS or META. The current version of this patch depends on a patch[1] which exists in drm-misc-fixes, but has not yet made it back to drm-misc-next (the target of this patch). That patch adds the function pvr_vm_unmap_obj() which is used here. [1]: https://lore.kernel.org/r/20250226-hold-drm_gem_gpuva-lock-for-unmap-v2-1-3fdacded227f@imgtec.com Signed-off-by: Sarah Walker Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-14-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/Makefile | 1 + drivers/gpu/drm/imagination/pvr_fw.c | 18 +- drivers/gpu/drm/imagination/pvr_fw.h | 10 ++ drivers/gpu/drm/imagination/pvr_fw_riscv.c | 165 ++++++++++++++++++ .../gpu/drm/imagination/pvr_fw_startstop.c | 17 ++ drivers/gpu/drm/imagination/pvr_rogue_riscv.h | 41 +++++ 6 files changed, 244 insertions(+), 8 deletions(-) create mode 100644 drivers/gpu/drm/imagination/pvr_fw_riscv.c create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_riscv.h diff --git a/drivers/gpu/drm/imagination/Makefile b/drivers/gpu/drm/imagination/Makefile index f45782063f43..7cca66f00a38 100644 --- a/drivers/gpu/drm/imagination/Makefile +++ b/drivers/gpu/drm/imagination/Makefile @@ -12,6 +12,7 @@ powervr-y := \ pvr_fw.o \ pvr_fw_meta.o \ pvr_fw_mips.o \ + pvr_fw_riscv.o \ pvr_fw_startstop.o \ pvr_fw_trace.o \ pvr_fw_util.o \ diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagination/pvr_fw.c index 962b8cb2119e..b2f8cba77346 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -941,7 +941,7 @@ pvr_fw_init(struct pvr_device *pvr_dev) static const struct pvr_fw_defs *fw_defs[PVR_FW_PROCESSOR_TYPE_COUNT] = { [PVR_FW_PROCESSOR_TYPE_META] = &pvr_fw_defs_meta, [PVR_FW_PROCESSOR_TYPE_MIPS] = &pvr_fw_defs_mips, - [PVR_FW_PROCESSOR_TYPE_RISCV] = NULL, + [PVR_FW_PROCESSOR_TYPE_RISCV] = &pvr_fw_defs_riscv, }; u32 kccb_size_log2 = ROGUE_FWIF_KCCB_NUMCMDS_LOG2_DEFAULT; @@ -954,13 +954,6 @@ pvr_fw_init(struct pvr_device *pvr_dev) fw_dev->defs = fw_defs[fw_dev->processor_type]; - /* - * Not all firmware processor types are currently supported. - * Once they are, this check can be removed. - */ - if (!fw_dev->defs) - return -EINVAL; - err = fw_dev->defs->init(pvr_dev); if (err) return err; @@ -1466,6 +1459,15 @@ void pvr_fw_object_get_fw_addr_offset(struct pvr_fw_object *fw_obj, u32 offset, *fw_addr_out = pvr_dev->fw_dev.defs->get_fw_addr_with_offset(fw_obj, offset); } +u64 +pvr_fw_obj_get_gpu_addr(struct pvr_fw_object *fw_obj) +{ + struct pvr_device *pvr_dev = to_pvr_device(gem_from_pvr_gem(fw_obj->gem)->dev); + struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev; + + return fw_dev->fw_heap_info.gpu_addr + fw_obj->fw_addr_offset; +} + /* * pvr_fw_hard_reset() - Re-initialise the FW code and data segments, and reset all global FW * structures diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h index e120eae06bf7..1404dd492d7c 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -392,6 +392,7 @@ enum pvr_fw_processor_type { extern const struct pvr_fw_defs pvr_fw_defs_meta; extern const struct pvr_fw_defs pvr_fw_defs_mips; +extern const struct pvr_fw_defs pvr_fw_defs_riscv; int pvr_fw_validate_init_device_info(struct pvr_device *pvr_dev); int pvr_fw_init(struct pvr_device *pvr_dev); @@ -478,6 +479,15 @@ pvr_fw_object_get_fw_addr(struct pvr_fw_object *fw_obj, u32 *fw_addr_out) pvr_fw_object_get_fw_addr_offset(fw_obj, 0, fw_addr_out); } +u64 +pvr_fw_obj_get_gpu_addr(struct pvr_fw_object *fw_obj); + +static __always_inline size_t +pvr_fw_obj_get_object_size(struct pvr_fw_object *fw_obj) +{ + return pvr_gem_object_size(fw_obj->gem); +} + /* Util functions defined in pvr_fw_util.c. These are intended for use in pvr_fw_.c files. */ int pvr_fw_process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code_ptr, diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv.c b/drivers/gpu/drm/imagination/pvr_fw_riscv.c new file mode 100644 index 000000000000..fc13d483be9a --- /dev/null +++ b/drivers/gpu/drm/imagination/pvr_fw_riscv.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* Copyright (c) 2024 Imagination Technologies Ltd. */ + +#include "pvr_device.h" +#include "pvr_fw.h" +#include "pvr_fw_info.h" +#include "pvr_fw_mips.h" +#include "pvr_gem.h" +#include "pvr_rogue_cr_defs.h" +#include "pvr_rogue_riscv.h" +#include "pvr_vm.h" + +#include +#include +#include +#include +#include + +#define ROGUE_FW_HEAP_RISCV_SHIFT 25 /* 32 MB */ +#define ROGUE_FW_HEAP_RISCV_SIZE (1u << ROGUE_FW_HEAP_RISCV_SHIFT) + +static int +pvr_riscv_wrapper_init(struct pvr_device *pvr_dev) +{ + const u64 common_opts = + ((u64)(ROGUE_FW_HEAP_RISCV_SIZE >> FWCORE_ADDR_REMAP_CONFIG0_SIZE_ALIGNSHIFT) + << ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_SHIFT) | + ((u64)MMU_CONTEXT_MAPPING_FWPRIV + << FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_SHIFT); + + u64 code_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.code_obj); + u64 data_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.data_obj); + + /* This condition allows us to OR the addresses into the register directly. */ + static_assert(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_SHIFT == + ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSHIFT); + + WARN_ON(code_addr & ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK); + WARN_ON(data_addr & ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK); + + pvr_cr_write64(pvr_dev, ROGUE_RISCVFW_REGION_REMAP_CR(BOOTLDR_CODE), + code_addr | common_opts | ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_EN); + + pvr_cr_write64(pvr_dev, ROGUE_RISCVFW_REGION_REMAP_CR(BOOTLDR_DATA), + data_addr | common_opts | + ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_EN); + + /* Garten IDLE bit controlled by RISC-V. */ + pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG, + ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META); + + return 0; +} + +struct rogue_riscv_fw_boot_data { + u64 coremem_code_dev_vaddr; + u64 coremem_data_dev_vaddr; + u32 coremem_code_fw_addr; + u32 coremem_data_fw_addr; + u32 coremem_code_size; + u32 coremem_data_size; + u32 flags; + u32 reserved; +}; + +static int +pvr_riscv_fw_process(struct pvr_device *pvr_dev, const u8 *fw, + u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr, + u32 core_code_alloc_size) +{ + struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev; + struct pvr_fw_mem *fw_mem = &fw_dev->mem; + struct rogue_riscv_fw_boot_data *boot_data; + int err; + + err = pvr_fw_process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr, + fw_core_code_ptr, fw_core_data_ptr); + if (err) + goto err_out; + + boot_data = (struct rogue_riscv_fw_boot_data *)fw_data_ptr; + + if (fw_mem->core_code_obj) { + boot_data->coremem_code_dev_vaddr = pvr_fw_obj_get_gpu_addr(fw_mem->core_code_obj); + pvr_fw_object_get_fw_addr(fw_mem->core_code_obj, &boot_data->coremem_code_fw_addr); + boot_data->coremem_code_size = pvr_fw_obj_get_object_size(fw_mem->core_code_obj); + } + + if (fw_mem->core_data_obj) { + boot_data->coremem_data_dev_vaddr = pvr_fw_obj_get_gpu_addr(fw_mem->core_data_obj); + pvr_fw_object_get_fw_addr(fw_mem->core_data_obj, &boot_data->coremem_data_fw_addr); + boot_data->coremem_data_size = pvr_fw_obj_get_object_size(fw_mem->core_data_obj); + } + + return 0; + +err_out: + return err; +} + +static int +pvr_riscv_init(struct pvr_device *pvr_dev) +{ + pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_RISCV_SHIFT, 0); + + return 0; +} + +static u32 +pvr_riscv_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset) +{ + u32 fw_addr = fw_obj->fw_addr_offset + offset; + + /* RISC-V cacheability is determined by address. */ + if (fw_obj->gem->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED) + fw_addr |= ROGUE_RISCVFW_REGION_BASE(SHARED_UNCACHED_DATA); + else + fw_addr |= ROGUE_RISCVFW_REGION_BASE(SHARED_CACHED_DATA); + + return fw_addr; +} + +static int +pvr_riscv_vm_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj) +{ + struct pvr_gem_object *pvr_obj = fw_obj->gem; + + return pvr_vm_map(pvr_dev->kernel_vm_ctx, pvr_obj, 0, fw_obj->fw_mm_node.start, + pvr_gem_object_size(pvr_obj)); +} + +static void +pvr_riscv_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj) +{ + struct pvr_gem_object *pvr_obj = fw_obj->gem; + + pvr_vm_unmap_obj(pvr_dev->kernel_vm_ctx, pvr_obj, + fw_obj->fw_mm_node.start, fw_obj->fw_mm_node.size); +} + +static bool +pvr_riscv_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_IRQ_OS0_EVENT_STATUS) & + ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_EN; +} + +static void +pvr_riscv_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_IRQ_OS0_EVENT_CLEAR, + ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_EN); +} + +const struct pvr_fw_defs pvr_fw_defs_riscv = { + .init = pvr_riscv_init, + .fw_process = pvr_riscv_fw_process, + .vm_map = pvr_riscv_vm_map, + .vm_unmap = pvr_riscv_vm_unmap, + .get_fw_addr_with_offset = pvr_riscv_get_fw_addr_with_offset, + .wrapper_init = pvr_riscv_wrapper_init, + .irq_pending = pvr_riscv_irq_pending, + .irq_clear = pvr_riscv_irq_clear, + .has_fixed_data_addr = false, +}; diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c index 36cec227cfe3..dcbb9903e791 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c +++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c @@ -49,6 +49,14 @@ rogue_bif_init(struct pvr_device *pvr_dev) pvr_cr_write64(pvr_dev, BIF_CAT_BASEX(MMU_CONTEXT_MAPPING_FWPRIV), pc_addr); + + if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_RISCV) { + pc_addr = (((u64)pc_dma_addr >> ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSHIFT) + << ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_SHIFT) & + ~ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_CLRMSK; + + pvr_cr_write64(pvr_dev, FWCORE_MEM_CAT_BASEX(MMU_CONTEXT_MAPPING_FWPRIV), pc_addr); + } } static int @@ -114,6 +122,9 @@ pvr_fw_start(struct pvr_device *pvr_dev) (void)pvr_cr_read32(pvr_dev, ROGUE_CR_SYS_BUS_SECURE); /* Fence write */ } + if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_RISCV) + pvr_cr_write32(pvr_dev, ROGUE_CR_FWCORE_BOOT, 0); + /* Set Rogue in soft-reset. */ pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, soft_reset_mask); if (has_reset2) @@ -167,6 +178,12 @@ pvr_fw_start(struct pvr_device *pvr_dev) /* ... and afterwards. */ udelay(3); + if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_RISCV) { + /* Boot the FW. */ + pvr_cr_write32(pvr_dev, ROGUE_CR_FWCORE_BOOT, 1); + udelay(3); + } + return 0; err_reset: diff --git a/drivers/gpu/drm/imagination/pvr_rogue_riscv.h b/drivers/gpu/drm/imagination/pvr_rogue_riscv.h new file mode 100644 index 000000000000..9a070e24fa6a --- /dev/null +++ b/drivers/gpu/drm/imagination/pvr_rogue_riscv.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* Copyright (c) 2024 Imagination Technologies Ltd. */ + +#ifndef PVR_ROGUE_RISCV_H +#define PVR_ROGUE_RISCV_H + +#include "pvr_rogue_cr_defs.h" + +#include +#include +#include + +#define ROGUE_RISCVFW_REGION_SIZE SZ_256M +#define ROGUE_RISCVFW_REGION_SHIFT __ffs(ROGUE_RISCVFW_REGION_SIZE) + +enum rogue_riscvfw_region { + ROGUE_RISCV_REGION__RESERVED_0 = 0, + ROGUE_RISCV_REGION__RESERVED_1, + ROGUE_RISCV_REGION_SOCIF, + ROGUE_RISCV_REGION__RESERVED_3, + ROGUE_RISCV_REGION__RESERVED_4, + ROGUE_RISCV_REGION_BOOTLDR_DATA, + ROGUE_RISCV_REGION_SHARED_CACHED_DATA, + ROGUE_RISCV_REGION__RESERVED_7, + ROGUE_RISCV_REGION_COREMEM, + ROGUE_RISCV_REGION__RESERVED_9, + ROGUE_RISCV_REGION__RESERVED_A, + ROGUE_RISCV_REGION__RESERVED_B, + ROGUE_RISCV_REGION_BOOTLDR_CODE, + ROGUE_RISCV_REGION_SHARED_UNCACHED_DATA, + ROGUE_RISCV_REGION__RESERVED_E, + ROGUE_RISCV_REGION__RESERVED_F, + + ROGUE_RISCV_REGION__COUNT, +}; + +#define ROGUE_RISCVFW_REGION_BASE(r) ((u32)(ROGUE_RISCV_REGION_##r) << ROGUE_RISCVFW_REGION_SHIFT) +#define ROGUE_RISCVFW_REGION_REMAP_CR(r) \ + (ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 + (u32)(ROGUE_RISCV_REGION_##r) * 8U) + +#endif /* PVR_ROGUE_RISCV_H */ -- 2.51.0 From f0a1ab65d90420f2817569bbf67111feb8e6821e Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:14 +0100 Subject: [PATCH 16/16] drm/imagination: Use cached memory with dma_coherent The TI k3-j721s2 platform does not allow us to use uncached memory (which is what the driver currently does) without disabling cache snooping on the AXI ACE-Lite interface, which would be too much of a performance hit. Given the platform is dma-coherent, we can simply force all device-accessible memory allocations through the CPU cache. In fact, this can be done whenever the dma_coherent attribute is present. Reviewed-by: Frank Binns Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-15-eda620c5865f@imgtec.com Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_gem.c | 10 +++++++--- drivers/gpu/drm/imagination/pvr_gem.h | 6 ++++-- drivers/gpu/drm/imagination/pvr_mmu.c | 8 +++++++- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_gem.c b/drivers/gpu/drm/imagination/pvr_gem.c index f692a4187550..a66cf082af24 100644 --- a/drivers/gpu/drm/imagination/pvr_gem.c +++ b/drivers/gpu/drm/imagination/pvr_gem.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -334,6 +335,7 @@ struct drm_gem_object *pvr_gem_create_object(struct drm_device *drm_dev, size_t struct pvr_gem_object * pvr_gem_object_create(struct pvr_device *pvr_dev, size_t size, u64 flags) { + struct drm_device *drm_dev = from_pvr_device(pvr_dev); struct drm_gem_shmem_object *shmem_obj; struct pvr_gem_object *pvr_obj; struct sg_table *sgt; @@ -343,7 +345,10 @@ pvr_gem_object_create(struct pvr_device *pvr_dev, size_t size, u64 flags) if (size == 0 || !pvr_gem_object_flags_validate(flags)) return ERR_PTR(-EINVAL); - shmem_obj = drm_gem_shmem_create(from_pvr_device(pvr_dev), size); + if (device_get_dma_attr(drm_dev->dev) == DEV_DMA_COHERENT) + flags |= PVR_BO_CPU_CACHED; + + shmem_obj = drm_gem_shmem_create(drm_dev, size); if (IS_ERR(shmem_obj)) return ERR_CAST(shmem_obj); @@ -358,8 +363,7 @@ pvr_gem_object_create(struct pvr_device *pvr_dev, size_t size, u64 flags) goto err_shmem_object_free; } - dma_sync_sgtable_for_device(shmem_obj->base.dev->dev, sgt, - DMA_BIDIRECTIONAL); + dma_sync_sgtable_for_device(drm_dev->dev, sgt, DMA_BIDIRECTIONAL); /* * Do this last because pvr_gem_object_zero() requires a fully diff --git a/drivers/gpu/drm/imagination/pvr_gem.h b/drivers/gpu/drm/imagination/pvr_gem.h index e0e5ea509a2e..c99f30cc6208 100644 --- a/drivers/gpu/drm/imagination/pvr_gem.h +++ b/drivers/gpu/drm/imagination/pvr_gem.h @@ -44,8 +44,10 @@ struct pvr_file; * Bits not defined anywhere are "undefined". * * CPU mapping options - * :PVR_BO_CPU_CACHED: By default, all GEM objects are mapped write-combined on the CPU. Set this - * flag to override this behaviour and map the object cached. + * :PVR_BO_CPU_CACHED: By default, all GEM objects are mapped write-combined on the CPU. Set + * this flag to override this behaviour and map the object cached. If the dma_coherent + * property is present in devicetree, all allocations will be mapped as if this flag was set. + * This does not require any additional consideration at allocation time. * * Firmware options * :PVR_BO_FW_NO_CLEAR_ON_RESET: By default, all FW objects are cleared and reinitialised on hard diff --git a/drivers/gpu/drm/imagination/pvr_mmu.c b/drivers/gpu/drm/imagination/pvr_mmu.c index 4fe70610ed94..450d476d183f 100644 --- a/drivers/gpu/drm/imagination/pvr_mmu.c +++ b/drivers/gpu/drm/imagination/pvr_mmu.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #define PVR_SHIFT_FROM_SIZE(size_) (__builtin_ctzll(size_)) @@ -259,6 +260,7 @@ pvr_mmu_backing_page_init(struct pvr_mmu_backing_page *page, struct device *dev = from_pvr_device(pvr_dev)->dev; struct page *raw_page; + pgprot_t prot; int err; dma_addr_t dma_addr; @@ -268,7 +270,11 @@ pvr_mmu_backing_page_init(struct pvr_mmu_backing_page *page, if (!raw_page) return -ENOMEM; - host_ptr = vmap(&raw_page, 1, VM_MAP, pgprot_writecombine(PAGE_KERNEL)); + prot = PAGE_KERNEL; + if (device_get_dma_attr(dev) != DEV_DMA_COHERENT) + prot = pgprot_writecombine(prot); + + host_ptr = vmap(&raw_page, 1, VM_MAP, prot); if (!host_ptr) { err = -ENOMEM; goto err_free_page; -- 2.51.0