From 1c9b0c6044c22835e2998d270ecca8a636e30294 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:26 -0400 Subject: [PATCH 01/16] arm64: dts: imx8: use common imx-pcie0-ep.dtso to enable PCI ep function Use common imx-pcie0-ep.dtso for imx8mp-evk-pcie-ep and imx8qxp-mek-pcie-ep. No functional change. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 8 +++++-- ...8mp-evk-pcie-ep.dtso => imx-pcie0-ep.dtso} | 6 ++--- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 8 ++++++- .../dts/freescale/imx8qxp-mek-pcie-ep.dtso | 22 ------------------- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 11 +++++++++- 5 files changed, 25 insertions(+), 30 deletions(-) rename arch/arm64/boot/dts/freescale/{imx8mp-evk-pcie-ep.dtso => imx-pcie0-ep.dtso} (64%) delete mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 186101781440..4f50cd5aa0f7 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -104,6 +104,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb + +imx8dxl-evk-pcie-ep-dtbs += imx8dxl-evk.dtb imx-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb @@ -239,7 +243,7 @@ imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds- imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtbo imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-lvds-hdmi.dtbo imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo -imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx8mp-evk-pcie-ep.dtbo +imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-lvds-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb @@ -286,7 +290,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb -imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx8qxp-mek-pcie-ep.dtbo +imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso b/arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso similarity index 64% rename from arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso rename to arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso index 244e820699b5..ed73284d9bb6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso +++ b/arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso @@ -6,12 +6,10 @@ /dts-v1/; /plugin/; -&pcie { +&pcie0 { status = "disabled"; }; -&pcie_ep { - pinctrl-0 = <&pinctrl_pcie0>; - pinctrl-names = "default"; +&pcie0_ep { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 9ab3ee93a35b..1ba3018c621e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -711,7 +711,7 @@ status = "okay"; }; -&pcie { +&pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; @@ -719,6 +719,12 @@ status = "okay"; }; +&pcie0_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + status = "disabled"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso deleted file mode 100644 index 4f562eb5c5b1..000000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2025 NXP - */ - -#include - -/dts-v1/; -/plugin/; - -&pcieb { - status = "disabled"; -}; - -&pcieb_ep { - phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; - phy-names = "pcie-phy"; - pinctrl-0 = <&pinctrl_pcieb>; - pinctrl-names = "default"; - vpcie-supply = <®_pcieb>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 4ba8ddd47223..c93d123670bd 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -537,7 +537,7 @@ status = "okay"; }; -&pcieb { +&pcie0 { phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; @@ -547,6 +547,15 @@ status = "okay"; }; +&pcie0_ep { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + vpcie-supply = <®_pcieb>; + status = "disabled"; +}; + &scu_key { status = "okay"; }; -- 2.51.0 From 58bea81052d0bf6e8fc438dda361569b72d3e8f1 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:27 -0400 Subject: [PATCH 02/16] arm64: dts: imx95: add pcie1 ep overlay file and create pcie-ep dtb files Create imx95-15x15-evk pcie0-ep and imx95-19x19-evk pcie[0,1]-ep dtb files. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 6 ++++++ arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso | 15 +++++++++++++++ arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 7 +++++++ arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 14 ++++++++++++++ 4 files changed, 42 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 4f50cd5aa0f7..51a97fd1dd58 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -312,6 +312,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb +imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb +imx95-19x19-evk-pcie0-ep-dtbs += imx95-19x19-evk.dtb imx-pcie0-ep.dtbo +imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep.dtb + imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb diff --git a/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso b/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso new file mode 100644 index 000000000000..0e7ef7ef8560 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; +/plugin/; + +&pcie1 { + status = "disabled"; +}; + +&pcie1_ep { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index aa0b9a4c3688..6c47f4b47356 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -534,6 +534,13 @@ status = "okay"; }; +&pcie0_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + vpcie-supply = <®_m2_pwr>; + status = "disabled"; +}; + &sai1 { assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index a41d542488ed..6886ea766655 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -426,6 +426,13 @@ status = "okay"; }; +&pcie0_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + vpcie-supply = <®_pcie0>; + status = "disabled"; +}; + &pcie1 { pinctrl-0 = <&pinctrl_pcie1>; pinctrl-names = "default"; @@ -434,6 +441,13 @@ status = "okay"; }; +&pcie1_ep { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + vpcie-supply = <®_slot_pwr>; + status = "disabled"; +}; + &sai1 { #sound-dai-cells = <0>; pinctrl-names = "default"; -- 2.51.0 From a705eb167ca4abd62b24540bcde19c592730caee Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:28 -0400 Subject: [PATCH 03/16] arm64: dts: imx8mm-evk: add pcie0-ep node and apply pcie0-ep overlay file Add pcie0-ep node information and apply pcie0-ep overlay file. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 5 +++++ arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 51a97fd1dd58..995f03ed28c9 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -116,6 +116,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb + +imx8mm-evk-pcie-ep-dtbs += imx8mm-evk.dtb imx-pcie0-ep.dtbo +imx8mm-evkb-pcie-ep-dtbs += imx8mm-evkb.dtb imx-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 5f8336217bb8..622caaa78eaf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -544,6 +544,19 @@ status = "okay"; }; +&pcie0_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "disabled"; +}; + &sai2 { #sound-dai-cells = <0>; pinctrl-names = "default"; -- 2.51.0 From 627b791541204a365ec64d4609ba3a98ff3aaccb Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:29 -0400 Subject: [PATCH 04/16] arm64: dts: imx8mq: add pcie0-ep node Add pcie0-ep node for i.MX8QM. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 07925b387677..c9040d1131a8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1770,6 +1770,41 @@ status = "disabled"; }; + pcie0_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mq-pcie-ep"; + reg = <0x33800000 0x100000>, + <0x18000000 0x8000000>, + <0x33900000 0x100000>, + <0x33b00000 0x100000>; + reg-names = "dbi", "addr_space", "dbi2", "atu"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + linux,pci-domain = <0>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; + num-ib-windows = <4>; + num-ob-windows = <4>; + fsl,max-link-speed = <2>; + status = "disabled"; + }; + pcie1: pcie@33c00000 { compatible = "fsl,imx8mq-pcie"; reg = <0x33c00000 0x400000>, -- 2.51.0 From 6e94adb40a8a24a4cc54459a13b6ca0de8f2fd04 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:30 -0400 Subject: [PATCH 05/16] arm64: dts: imx8mq-evk: add pcie[0,1]-ep nodes Add pcie[0,1]-ep nodes and apply imx-pcie1-ep overlay file. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 3 +++ arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 995f03ed28c9..90652292a911 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -262,6 +262,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb +imx8mq-evk-pcie1-ep-dtbs += imx8mq-evk.dtb imx-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-pcie1-ep.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index a87d0692c3bb..43e45b0bd0d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -377,6 +377,16 @@ status = "okay"; }; +&pcie0_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&pcie0_refclk>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_AUX>; + status = "disabled"; +}; + &pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie1>; @@ -390,6 +400,16 @@ status = "okay"; }; +&pcie1_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&pcie0_refclk>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + status = "disabled"; +}; + &pgc_gpu { power-supply = <&sw1a_reg>; }; -- 2.51.0 From 95727d056c8f5cad668c1f5711b25102b474216f Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Thu, 17 Apr 2025 14:01:13 +0200 Subject: [PATCH 06/16] arm64: dts: add imx8mp-libra-rdk-fpsc board Add device tree for the Libra-i.MX 8M Plus FPSC board. The Libra is a pure development board and has hardware to support FPSC-24-A.0 set of features. It can be populated with the phyCORE-i.MX 8M Plus SoM to form a SBC. The phyCORE-i.MX 8M Plus FPSC [1] SoM uses only a subset of the hardware features the Libra board provides. The phyCORE-i.MX8MP FPSC itself is a System on Module based on the i.MX 8M Plus SoC utilizing the Future Proof Solder Core [2] standard. To be able to easily map FPSC interface names to SoC interfaces, the FPSC interface names are added as inline comments. Example: &i2c5 { /* FPSC I2C4 */ pinctrl-0 = <&pinctrl_i2c5>; [...] }; Here, I2C4 is the FPSC interface name. The i2c5 instance of the i.MX 8M Plus SoC is used to fulfill the i2c functionality and its signals are routed to the FPSC I2C4 signal pins: pinctrl_i2c5: i2c5grp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 /* I2C4_SDA */ MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 /* I2C4_SCL */ >; }; The features are almost identical to the existing phyCORE-i.MX 8M Plus SoM (dts: imx8mp-phycore-som.dtsi), but the pin muxing is different due to the FPSC standard as well as 1.8V IO voltage instead of 3.3V. [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/ [2] https://www.phytec.eu/en/produkte/system-on-modules/fpsc/ Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-libra-rdk-fpsc.dts | 290 +++++++ .../dts/freescale/imx8mp-phycore-fpsc.dtsi | 796 ++++++++++++++++++ 3 files changed, 1087 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 90652292a911..4ec67b438e82 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -209,6 +209,7 @@ imx8mp-kontron-dl-dtbs += imx8mp-kontron-bl-osm-s.dtb imx8mp-kontron-dl.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts new file mode 100644 index 000000000000..6f3a7b863dca --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; + +#include +#include +#include +#include "imx8mp-phycore-fpsc.dtsi" + +/ { + compatible = "phytec,imx8mp-libra-rdk-fpsc", + "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp"; + model = "PHYTEC i.MX8MP Libra RDK FPSC"; + + backlight_lvds0: backlight0 { + compatible = "pwm-backlight"; + pinctrl-0 = <&pinctrl_lvds0>; + pinctrl-names = "default"; + power-supply = <®_vdd_12v0>; + status = "disabled"; + }; + + chosen { + stdout-path = &uart4; + }; + + panel0_lvds: panel-lvds { + /* compatible panel in overlay */ + backlight = <&backlight_lvds0>; + power-supply = <®_vdd_3v3>; + status = "disabled"; + + port { + panel0_in: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "can1-stby"; + gpio = <&gpio_expander 10 GPIO_ACTIVE_LOW>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "can2-stby"; + gpio = <&gpio_expander 9 GPIO_ACTIVE_LOW>; + }; + + reg_vdd_12v0: regulator-vdd-12v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "VDD_12V0"; + }; + + reg_vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8"; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3"; + }; + + reg_vdd_5v0: regulator-vdd-5v0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "VDD_5V0"; + }; +}; + +&eqos { + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + enet-phy-lane-no-swap; + ti,clk-output-sel = ; + ti,fifo-depth = ; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; + }; +}; + +/* CAN FD */ +&flexcan1 { + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&flexspi { + status = "okay"; + + spi_nor: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <®_vdd_1v8>; + }; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", "I2C5_SDA", + "GPIO1", "", "", "", "SPI1_CS", + "", "", "", "SPI2_CS", "I2C1_SCL", + "I2C1_SDA", "I2C2_SCL", "I2C2_SDA", "I2C3_SCL", "I2C3_SDA", + "", "GPIO2", "", "LVDS1_BL_EN", "SPI3_CS", + "", "GPIO3"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + vcc-supply = <®_vdd_1v8>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + leds@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-1 { + type = ; + }; + + led-2 { + type = ; + }; + + led-3 { + type = ; + }; + }; +}; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "CSI1_CTRL1", "CSI1_CTRL2", "CSI1_CTRL3", + "CSI1_CTRL4", "CSI2_CTRL1", "CSI2_CTRL2", + "CSI2_CTRL3", "CSI2_CTRL4", "CLK_EN_AV", + "nCAN2_EN", "nCAN1_EN", "PCIE1_nWAKE", + "PCIE2_nWAKE", "PCIE2_nALERT_3V3", + "UART1_BT_RS_SEL", "UART1_RS232_485_SEL"; + vcc-supply = <®_vdd_1v8>; + + uart1_bt_rs_sel: bt-rs-hog { + gpios = <14 GPIO_ACTIVE_HIGH>; + gpio-hog; + line-name = "UART1_BT_RS_SEL"; + output-low; /* default RS232/RS485 */ + }; + + uart1_rs232_485_sel: rs232-485-hog { + gpios = <15 GPIO_ACTIVE_HIGH>; + gpio-hog; + line-name = "UART1_RS232_485_SEL"; + output-high; /* default RS232 */ + }; + }; +}; + +&iomuxc { + pinctrl_lvds0: lvds0grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x12 + >; + }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1C0 + >; + }; +}; + +&lvds_bridge { + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +/* Mini PCIe */ +&pcie { + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_vdd_3v3>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +®_vdd_io { + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; +}; + +&rv3028 { + interrupt-parent = <&gpio5>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + aux-voltage-chargeable = <1>; + pinctrl-0 = <&pinctrl_rtc>; + pinctrl-names = "default"; + trickle-resistor-ohms = <3000>; + wakeup-source; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* debug console */ +&uart4 { + status = "okay"; +}; + +/* SD-Card */ +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + disable-wp; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi new file mode 100644 index 000000000000..8b0e8cf86cad --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi @@ -0,0 +1,796 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include "imx8mp.dtsi" + +/ { + compatible = "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp"; + model = "PHYTEC phyCORE-i.MX8MP FPSC"; + + aliases { + rtc0 = &rv3028; + rtc1 = &snvs_rtc; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x80000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDDSW_SD2"; + startup-delay-us = <100>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vdd_io: regulator-vdd-io { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "VDD_IO"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ecspi1 { /* FPSC SPI1 */ + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-names = "default"; +}; + +&ecspi2 { /* FPSC SPI2 */ + pinctrl-0 = <&pinctrl_ecspi2>; + pinctrl-names = "default"; +}; + +&ecspi3 { /* FPSC SPI3 */ + pinctrl-0 = <&pinctrl_ecspi3>; + pinctrl-names = "default"; +}; + +&eqos { /* FPSC RGMII2 */ + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-names = "default"; +}; + +&fec { /* FPSC GB_ETH1 */ + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-names = "default"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,clk-output-sel = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; + }; +}; + +&flexcan1 { /* FPSC CAN1 */ + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-names = "default"; +}; + +&flexcan2 { /* FPSC CAN2 */ + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; +}; + +&flexspi { /* FPSC QSPI */ + pinctrl-0 = <&pinctrl_flexspi>; + pinctrl-names = "default"; +}; + +&gpio1 { + gpio-line-names = "", "", "", "", "", + "", "", "", "PCIE1_nPERST"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "SD2_RESET_B"; +}; + +&gpio3 { + gpio-line-names = "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "I2C6_SCL", + "I2C6_SDA", "I2C5_SCL"; +}; + +&gpio4 { /* FPSC GPIO */ + gpio-line-names = "GPIO6", "RGMII2_nINT", "GPIO7", "GPIO4", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "X_PMIC_IRQ_B", "", + "", "GPIO5", "", "", "RGMII2_EVENT_OUT", + "", "", "RGMII2_EVENT_IN"; + pinctrl-0 = <&pinctrl_gpio4>; + pinctrl-names = "default"; +}; + +&gpio5 { /* FPSC GPIO */ + gpio-line-names = "", "", "", "", "I2C5_SDA", + "GPIO1", "", "", "", "SPI1_CS", + "", "", "", "SPI2_CS", "I2C1_SCL", + "I2C1_SDA", "I2C2_SCL", "I2C2_SDA", "I2C3_SCL", "I2C3_SDA", + "", "GPIO2", "", "", "SPI3_CS", + "", "GPIO3"; + pinctrl-0 = <&pinctrl_gpio5>; + pinctrl-names = "default"; +}; + +&i2c1 { /* FPSC I2C1 */ + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + + regulators { + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <850000>; + regulator-name = "VDD_SOC (BUCK1)"; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <850000>; + regulator-name = "VDD_ARM (BUCK2)"; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3 (BUCK4)"; + }; + + buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8 (BUCK5)"; + }; + + buck6: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; + regulator-name = "NVCC_DRAM_1V1 (BUCK6)"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SNVS_1V8 (LDO1)"; + }; + + ldo3: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDDA_1V8 (LDO3)"; + }; + + ldo5: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SD2 (LDO5)"; + }; + }; + }; + + /* User EEPROM */ + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <®_vdd_io>; + }; + + /* factory EEPROM */ + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + read-only; + vcc-supply = <®_vdd_io>; + }; + + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&i2c2 { /* FPSC I2C2 */ + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c3 { /* FPSC I2C3 */ + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c5 { /* FPSC I2C4 */ + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c6 { /* FPSC I2C5 */ + pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&iomuxc { + pinctrl_flexcan1: can1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 /* CAN1_TX */ + MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 /* CAN1_RX */ + >; + }; + + pinctrl_flexcan2: can2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 /* CAN2_TX */ + MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 /* CAN2_RX */ + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10 /* RGMII2_nINT */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10 /* RGMII2_EVENT_IN */ + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x10 /* RGMII2_EVENT_OUT */ + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 /* RGMII2_MDIO */ + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 /* RGMII2_MDC */ + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12 /* RGMII2_TX_D3 */ + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12 /* RGMII2_TX_D2 */ + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 /* RGMII2_TX_D1 */ + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 /* RGMII2_TX_D0 */ + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 /* RGMII2_TX_CTL */ + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12 /* RGMII2_TXC */ + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 /* RGMII2_RX_D3 */ + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 /* RGMII2_RX_D2 */ + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 /* RGMII2_RX_D1 */ + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 /* RGMII2_RX_D0 */ + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 /* RGMII2_RX_CTL */ + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 /* RGMII2_RXC */ + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + >; + }; + + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 /* QSPI_CE */ + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 /* QSPI_CLK */ + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 /* QSPI_DATA_0 */ + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 /* QSPI_DATA_1 */ + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 /* QSPI_DATA_2 */ + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 /* QSPI_DATA_3 */ + MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82 /* QSPI_DQS */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40 /* GPIO4 */ + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 /* GPIO5 */ + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x106 /* GPIO6 */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x106 /* GPIO7 */ + >; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x106 /* GPIO1 */ + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x106 /* GPIO2 */ + MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x106 /* GPIO3 */ + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x106 /* HDMI_CEC */ + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x106 /* HDMI_SCL */ + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x106 /* HDMI_SDA */ + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x106 /* HDMI_HPD */ + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2 + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 /* I2C1_SDA_DNU */ + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 /* I2C1_SCL_DNU */ + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 /* I2C2_SDA */ + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 /* I2C2_SCL */ + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1e2 + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1e2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 /* I2C3_SDA */ + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 /* I2C3_SCL */ + >; + }; + + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1e2 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1e2 + >; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 /* I2C4_SDA */ + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 /* I2C4_SCL */ + >; + }; + + pinctrl_i2c6_gpio: i2c6gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x1e2 + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x1e2 + >; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c2 /* I2C5_SDA */ + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c2 /* I2C5_SCL */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x10 /* PCIE1_nCLKREQ */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 /* PCIE1_nPERST */ + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x106 /* PWM1 */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x106 /* PWM2 */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x106 /* PWM3 */ + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x106 /* PWM4 */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x106 /* SAI1_MCLK */ + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x106 /* SAI1_RX_SYNC */ + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x106 /* SAI1_RX_BCLK */ + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x106 /* SAI1_RX_DATA */ + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x106 /* SAI1_TX_SYNC */ + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x106 /* SAI1_TX_BCLK */ + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x106 /* SAI1_TX_DATA */ + >; + }; + + pinctrl_ecspi1: spi1grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 /* SPI1_SCLK */ + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 /* SPI1_MOSI */ + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 /* SPI1_MISO */ + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x106 /* SPI1_CS */ + >; + }; + + pinctrl_ecspi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 /* SPI2_SCLK */ + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 /* SPI2_MOSI */ + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 /* SPI2_MISO */ + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x106 /* SPI2_CS */ + >; + }; + + pinctrl_ecspi3: spi3grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x82 /* SPI3_SCLK */ + MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x82 /* SPI3_MOSI */ + MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x82 /* SPI3_MISO */ + MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x106 /* SPI3_CS */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x140 /* UART2_RXD */ + MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x140 /* UART2_TXD */ + MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x140 /* UART2_RTS */ + MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x140 /* UART2_CTS */ + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x140 /* UART1_RXD */ + MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x140 /* UART1_TXD */ + MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x140 /* UART1_RTS */ + MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x140 /* UART1_CTS */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 /* UART3_RXD */ + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 /* UART3_TXD */ + >; + }; + + pinctrl_usb0: usb0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x106 /* USB1_PWR_EN */ + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x106 /* USB1_OC */ + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x106 /* USB1_ID */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x106 /* USB2_PWR_EN */ + MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x106 /* USB2_OC */ + MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x106 /* USB2_ID */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x106 /* SDIO_WP */ + MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x106 /* SDIO_CD */ + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x106 /* SDIO_CLK */ + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x106 /* SDIO_CLK */ + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x106 /* SDIO_DATA0 */ + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x106 /* SDIO_DATA1 */ + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x106 /* SDIO_DATA2 */ + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x106 /* SDIO_DATA3 */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */ + MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */ + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 /* SDCARD_CLK */ + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 /* SDCARD_CMD */ + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 /* SDCARD_DATA0 */ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDCARD_DATA1 */ + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDCARD_DATA2 */ + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDCARD_DATA3 */ + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */ + MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */ + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 /* SDCARD_CLK */ + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 /* SDCARD_CMD */ + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 /* SDCARD_DATA0 */ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDCARD_DATA1 */ + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDCARD_DATA2 */ + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDCARD_DATA3 */ + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */ + MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */ + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 /* SDCARD_CLK */ + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 /* SDCARD_CMD */ + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 /* SDCARD_DATA0 */ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDCARD_DATA1 */ + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDCARD_DATA2 */ + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDCARD_DATA3 */ + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 + >; + }; +}; + +&pcie { /* FPSC PCIE1 */ + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; +}; + +&pwm1 { /* FPSC PWM1 */ + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; +}; + +&pwm2 { /* FPSC PWM2 */ + pinctrl-0 = <&pinctrl_pwm2>; + pinctrl-names = "default"; +}; + +&pwm3 { /* FPSC PWM3 */ + pinctrl-0 = <&pinctrl_pwm3>; + pinctrl-names = "default"; +}; + +&pwm4 { /* FPSC PWM4 */ + pinctrl-0 = <&pinctrl_pwm4>; + pinctrl-names = "default"; +}; + +&sai5 { /* FPSC SAI1 */ + pinctrl-0 = <&pinctrl_sai5>; + pinctrl-names = "default"; +}; + +&uart2 { /* FPSC UART2 */ + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + fsl,dte-mode; +}; + +&uart3 { /* FPSC UART1 */ + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + fsl,dte-mode; +}; + +&uart4 { /* FPSC UART3 */ + pinctrl-0 = <&pinctrl_uart4>; + pinctrl-names = "default"; +}; + +&usb3_0 { /* FPSC USB1 */ + pinctrl-0 = <&pinctrl_usb0>; + pinctrl-names = "default"; +}; + +&usb3_1 { /* FPSC USB2 */ + pinctrl-0 = <&pinctrl_usb1>; + pinctrl-names = "default"; +}; + +&usdhc1 { /* FPSC SDIO */ + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default"; +}; + +&usdhc2 { /* FPSC SDCARD */ + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + sd-uhs-sdr104; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <&ldo5>; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&wdog1 { + pinctrl-0 = <&pinctrl_wdog>; + pinctrl-names = "default"; + fsl,ext-reset-output; + status = "okay"; +}; -- 2.51.0 From 2b743164ecfe906803f5632243549f897350f51e Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Thu, 17 Apr 2025 14:01:14 +0200 Subject: [PATCH 07/16] arm64: dts: add imx8mp-libra-rdk-fpsc LVDS panel overlay The Libra board has an LVDS connector. Add an overlay for an etml1010g3dra LVDS panel supported for the phyCORE-i.MX 8M Plus that may be connected to it. Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + ...8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso | 44 +++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 4ec67b438e82..d63000efdf27 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -210,6 +210,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc.dtb +imx8mp-libra-rdk-fpsc-lvds-dtbs += imx8mp-libra-rdk-fpsc.dtb imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso new file mode 100644 index 000000000000..1dcf249ca90d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&backlight_lvds0 { + brightness-levels = <0 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; + num-interpolated-steps = <2>; + pwms = <&pwm1 0 66667 0>; + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 72.4 MHz. + */ + assigned-clock-rates = <0>, <506800000>; + status = "okay"; +}; + +&panel0_lvds { + compatible = "edt,etml1010g3dra"; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; -- 2.51.0 From 98363ac3664001ed3990478ba09e87bd1820a892 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:30 +0200 Subject: [PATCH 08/16] arm64: dts: freescale: imx93-phycore-som: Add PMIC support PMIC driver for PCA9451A used on phyCORE-i.MX93 SOM is available since commit 5edeb7d31262 ("regulator: pca9450: add pca9451a support"). Add support for it in the SOM device-tree. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-phycore-som.dtsi | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 88c2657b50e6..507a71f9294b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -72,6 +72,90 @@ }; }; +/* I2C3 */ +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "VDD_SOC"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "VDDQ_0V6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3_BUCK"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "VDD_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "PMIC_SNVS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + /* eMMC */ &usdhc1 { pinctrl-names = "default"; @@ -108,6 +192,19 @@ >; }; + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e -- 2.51.0 From 31ff2efe6484000f103d5df0f32a4cb3a1dee06d Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:31 +0200 Subject: [PATCH 09/16] arm64: dts: freescale: imx93-phycore-som: Add EEPROM support Add support for the EEPROM chip available on I2C3 bus (address 0x50), used for the PHYTEC SOM detection. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 507a71f9294b..0528e293c03d 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -154,6 +154,14 @@ }; }; }; + + /* EEPROM */ + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <&buck4>; + }; }; /* eMMC */ -- 2.51.0 From d6241ba41f2c676b3f5a01497d99e5acb6ca2aef Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:32 +0200 Subject: [PATCH 10/16] arm64: dts: freescale: imx93-phycore-som: Disable LED pull-up There is already an external pull-down resistor on the LED output line. It makes no sense to have both pull-down and pull-up resistors enabled at the same time. Thus disable the internal pull-up. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 0528e293c03d..06a9e674e338 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -196,7 +196,7 @@ pinctrl_leds: ledsgrp { fsl,pins = < - MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x11e >; }; -- 2.51.0 From 54be09bdb1e7b6291eb9b99c5b60fc5026576bd1 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:33 +0200 Subject: [PATCH 11/16] arm64: dts: freescale: imx93-phycore-som: Enhance eMMC pinctrl Improve eMMC on phyCORE-i.MX93 SOM by adding 100MHz and 200MHz pinctrl modes. This enables to use eMMC at enhanced data rates (e.g. HS400). While at it, apply a workaround for the i.MX93 chip errata ERR052021. Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-phycore-som.dtsi | 57 +++++++++++++++---- 1 file changed, 47 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 06a9e674e338..663530a7e2bb 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -166,8 +166,10 @@ /* eMMC */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; status = "okay"; @@ -213,18 +215,53 @@ >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e - MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001386 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e >; }; -- 2.51.0 From 9ed135ca48391848766f61a37580737dcd86524f Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:34 +0200 Subject: [PATCH 12/16] arm64: dts: freescale: imx93-phycore-som: Add eMMC no-1-8-v by default The phyCORE-i.MX93 SoM comes in two variants, one with VDD_IO set to 3.3V and the other variant to 1.8V. The 3.3V variant can only support DDR52 mode, while 1.8V variant is capable of HS400ES eMMC mode. The information about VDD_IO option is encoded in the SoM's EEPROM. EEPROM is read in the bootloader and bootloader clears the "no-1-8-v" flag in case of 1.8V SoM variant is detected. Thus add property 'no-1-8-v' by default to usdhc1 (eMMC) node and let bootloader handle the flag. In case EEPROM is erased or read-out fails, flag "no-1-8-v" also ensures fall-back compatibility with both SoM variants. Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 663530a7e2bb..22dbcc89e311 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -172,6 +172,7 @@ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; + no-1-8-v; status = "okay"; }; -- 2.51.0 From bdd3071e10926847f4985056a0d80be88fc7cfd4 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:35 +0200 Subject: [PATCH 13/16] arm64: dts: freescale: imx93-phyboard-segin: Drop eMMC no-1-8-v flag Drop redundant 'no-1-8-v' flag from usdhc1 (eMMC) node. Flag is now set by default in the SOM include file (imx93-phycore-som.dtsi). Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 85fb188b057f..902b523fc92c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -40,11 +40,6 @@ status = "okay"; }; -/* eMMC */ -&usdhc1 { - no-1-8-v; -}; - /* SD-Card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; -- 2.51.0 From 99cf1026b7af5fa347aafd273f44494f52b0877c Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:36 +0200 Subject: [PATCH 14/16] arm64: dts: freescale: imx93-phyboard-segin: Disable SD-card write-protect Add disable-wp flag (write-protect) to usdhc2 node (SD-card) to get rid of the following kernel boot warning: host does not support reading read-only switch, assuming write-enable Micro SD cards can't be physically write-protected like full-sized cards anyways. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 902b523fc92c..3d5cd0561362 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -48,6 +48,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; bus-width = <4>; cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + disable-wp; no-mmc; no-sdio; vmmc-supply = <®_usdhc2_vmmc>; -- 2.51.0 From ff44686256ffb16a3bdb0c7600556d26ea7e0328 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:37 +0200 Subject: [PATCH 15/16] arm64: dts: freescale: imx93-phyboard-segin: Fix SD-card pinctrl Until now, all usdhc2 (SD-card) pinctrl labels pointed to one pinctrl group "usdhc2grp" which was overwritten twice by the 100 and 200 MHz modes. Fix this by using unique pinctrl names. Additionally, adjust MX93_PAD_SD2_CLK__USDHC2_CLK pad drive-strength according to values obtained by measurements from the PHYTEC hardware department to improve signal integrity. Signed-off-by: Primoz Fiser Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 3d5cd0561362..541297052b62 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -77,7 +77,7 @@ pinctrl_usdhc2_default: usdhc2grp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e @@ -87,9 +87,9 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e @@ -99,9 +99,9 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e -- 2.51.0 From d84fc1fc8e5e53afd95823bbc8450bb50ebec4a4 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 22 Apr 2025 12:56:38 +0200 Subject: [PATCH 16/16] arm64: dts: freescale: imx93-phyboard-segin: Set CMD/DATA SION bit to fix ERR052021 Implement fix for i.MX 93 silicon errata ERR052021. ERR052021 uSDHC: Sometimes uSDHC does not work under VDD_SOC low drive mode and nominal mode Description: uSDHC PADs have one integration issue. When CMD/DATA lines direction change from output to input, uSDHC controller begin sampling, the integration issue will make input enable signal from uSDHC propagated to the PAD with a long delay, thus the new input value on the pad comes to uSDHC lately. The uSDHC sampled the old input value and the sampling result is wrong. Workaround: Set uSDHC CMD/DATA PADs iomux register SION bit to 1, then PADs will propagate input to uSDHC with no delay, so correct value is sampled. This issue will wrongly trigger the start bit when sample the USDHC command response, cause the USDHC trigger command CRC/index/endbit error, which will finally impact the tuning pass window, especially will impact the standard tuning logic, and can't find a correct delay cell to get the best timing. Based on commit bb89601282fc ("arm64: dts: imx93-11x11-evk: set SION for cmd and data pad of USDHC"). Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-phyboard-segin.dts | 37 ++++++++++--------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 541297052b62..525f52789f8b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -75,39 +75,42 @@ >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_default: usdhc2grp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; }; -- 2.51.0