From 0af2f6be1b4281385b618cb86ad946eded089ac8 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sun, 6 Apr 2025 13:11:33 -0700 Subject: [PATCH 01/16] Linux 6.15-rc1 --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index e55726a71d95..38689a0c3605 100644 --- a/Makefile +++ b/Makefile @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 6 -PATCHLEVEL = 14 +PATCHLEVEL = 15 SUBLEVEL = 0 -EXTRAVERSION = +EXTRAVERSION = -rc1 NAME = Baby Opossum Posse # *DOCUMENTATION* -- 2.51.0 From 17268faf29992d37033d6ad1a5ed5d924f2430d8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:31:58 +0200 Subject: [PATCH 02/16] ARM: dts: qcom: msm8226: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-1-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 64c8ac94f352..c84320ef5ca2 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include #include @@ -983,8 +984,8 @@ <&gcc GPLL0_VOTE>, <&gcc GPLL1_VOTE>, <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>; + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; clock-names = "xo", "mmss_gpll0_vote", "gpll0_vote", @@ -1060,8 +1061,8 @@ assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, -- 2.51.0 From 1afdd80d1e021f758c975d857c6beb6da5c891bd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:31:59 +0200 Subject: [PATCH 03/16] ARM: dts: qcom: msm8974: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-2-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index e3f9c56a778c..7e119370f337 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -3,6 +3,7 @@ #include #include +#include #include #include #include @@ -1871,10 +1872,10 @@ <&gcc GPLL0_VOTE>, <&gcc GPLL1_VOTE>, <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi1_phy 1>, - <&mdss_dsi1_phy 0>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, <0>, <0>, <0>; @@ -1961,8 +1962,10 @@ interrupt-parent = <&mdss>; interrupts = <4>; - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, @@ -2032,8 +2035,10 @@ interrupt-parent = <&mdss>; interrupts = <4>; - assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, + <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, -- 2.51.0 From ae33b874fc81bfb60bdda5a350c0635f98e6d747 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:28 -0500 Subject: [PATCH 04/16] ARM: dts: qcom: sdx55/sdx65: Fix CPU power-domain-names "rpmhpd" is not documented nor used anywhere. The power-domain is used for performance scaling (cpufreq), so "perf" is the correct name to use. Signed-off-by: Rob Herring (Arm) Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250410-dt-cpu-schema-v2-7-63d7dc9ddd0a@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 39530eb580ea..20fdae9825e0 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -57,7 +57,7 @@ enable-method = "psci"; clocks = <&apcs>; power-domains = <&rpmhpd SDX55_CX>; - power-domain-names = "rpmhpd"; + power-domain-names = "perf"; operating-points-v2 = <&cpu_opp_table>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 6b23ee676c9e..c8e312dcd26b 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -58,7 +58,7 @@ enable-method = "psci"; clocks = <&apcs>; power-domains = <&rpmhpd SDX65_CX_AO>; - power-domain-names = "rpmhpd"; + power-domain-names = "perf"; operating-points-v2 = <&cpu_opp_table>; }; }; -- 2.51.0 From 3ea267124573f24e67f0fe47c4a865f0f283f8fc Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:30 -0500 Subject: [PATCH 05/16] ARM: dts: qcom: ipq4019: Drop redundant CPU "clock-latency" The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". The OPP table has values of 256000, so it can be removed. Signed-off-by: Rob Herring (Arm) Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250410-dt-cpu-schema-v2-9-63d7dc9ddd0a@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 06b20c196faf..fceb2f5f5482 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -53,7 +53,6 @@ reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -67,7 +66,6 @@ reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -81,7 +79,6 @@ reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -95,7 +92,6 @@ reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; -- 2.51.0 From cbcd04ab82c61dc777a4b56014292b9467f10c4e Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Thu, 8 May 2025 16:11:13 +0200 Subject: [PATCH 06/16] ARM: dts: qcom: msm8226-motorola-falcon: add clocks, power-domain to simpleFB Makes the display work without clk_ignore_unused and pd_ignore_unused. Signed-off-by: Stanislav Jakubek Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/cdb6915bf40c055c77a0beb2f49c20458adf7481.1746711762.git.stano.jakubek@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts index 5dbca83f2230..c01becca3d56 100644 --- a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts +++ b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts @@ -31,6 +31,15 @@ vsp-supply = <®_lcd_pos>; vsn-supply = <®_lcd_neg>; vddio-supply = <&vddio_disp_vreg>; + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + power-domains = <&mmcc MDSS_GDSC>; }; }; -- 2.51.0 From db6e3f2ba0bf6ad069347050ff62f29ef0d88b14 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Thu, 8 May 2025 16:11:19 +0200 Subject: [PATCH 07/16] ARM: dts: qcom: msm8226-motorola-falcon: add I2C clock frequencies While the currently supported hardware works fine with the default clock frequencies of 100000 on both I2C2 and I2C3, downstream sources list the frequencies as 100000 for I2C2 and 400000 for I2C3. Update them as such. Signed-off-by: Stanislav Jakubek Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/5a8191e3758e0df78b4213102f25ceadc28cd427.1746711762.git.stano.jakubek@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts index c01becca3d56..e2bf292159fa 100644 --- a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts +++ b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts @@ -106,6 +106,7 @@ }; &blsp1_i2c2 { + clock-frequency = <100000>; status = "okay"; magnetometer@c { @@ -135,6 +136,7 @@ }; &blsp1_i2c3 { + clock-frequency = <400000>; status = "okay"; regulator@3e { -- 2.51.0 From 7bce56fd73ee7264ed04418dab1719164e42f113 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Thu, 8 May 2025 16:11:27 +0200 Subject: [PATCH 08/16] ARM: dts: qcom: msm8226-motorola-falcon: limit TPS65132 to 5.4V After some digging in downstream sources, it was found that the TPS65132 outputs are fixed to +5.4V and -5.4V respectively. This is further confirmed on runtime through debugfs, the troubleshooting guide confirms this as well. Specify these limits as such. Signed-off-by: Stanislav Jakubek Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/b67ed6c7813fa52cf00b473dded9b5042102f593.1746711762.git.stano.jakubek@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts index e2bf292159fa..d6d5a86491aa 100644 --- a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts +++ b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts @@ -147,8 +147,8 @@ reg_lcd_pos: outp { regulator-name = "outp"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5400000>; regulator-active-discharge = <1>; regulator-boot-on; enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; @@ -156,8 +156,8 @@ reg_lcd_neg: outn { regulator-name = "outn"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5400000>; regulator-active-discharge = <1>; regulator-boot-on; enable-gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>; -- 2.51.0 From e41ece7cd173486f6767de050deb2d8f0882a82a Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Thu, 8 May 2025 16:11:34 +0200 Subject: [PATCH 09/16] ARM: dts: qcom: msm8226-motorola-falcon: specify vddio_disp output voltage After some digging in downstream sources, it was found that the vddio_disp regulator's output voltage is 1.8V. This is further confirmed by the troubleshooting guide. Specify its output voltage as such. While at it, add a comment specifying the IC, which according to the schematic is the TI TPS22902. Signed-off-by: Stanislav Jakubek Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/6143603464a65aebbed281fe6c6164316dd07269.1746711762.git.stano.jakubek@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts index d6d5a86491aa..e6392f7d14c7 100644 --- a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts +++ b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts @@ -62,9 +62,12 @@ }; }; + /* TI TPS22902 */ vddio_disp_vreg: regulator-vddio-disp { compatible = "regulator-fixed"; regulator-name = "vddio_disp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>; vin-supply = <&pm8226_l8>; startup-delay-us = <300>; -- 2.51.0 From 5e1be5d4617f68030eeab0532cf134948e19f5a2 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Tue, 18 Mar 2025 13:51:21 +0100 Subject: [PATCH 10/16] ARM: dts: qcom: apq8064-lg-nexus4-mako: Enable WiFi The Wi-Fi setup is identical to that of the Sony Xperia Z (Yuga). Verified against the legacy kernel configuration inside arch/arm/mach-msm/board-8064-regulator.c using LineageOS 14.1 kernel sources. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250318-lg-nexus4-mako-enable-wifi-v1-1-e3b4a09d9f68@ixit.cz Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-apq8064-lg-nexus4-mako.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts index 5710450faabf..c187c6875bc6 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts @@ -86,6 +86,24 @@ status = "okay"; }; +&riva { + pinctrl-names = "default"; + pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>; + + vddcx-supply = <&pm8921_s3>; + vddmx-supply = <&pm8921_l24>; + vddpx-supply = <&pm8921_s4>; + + status = "okay"; + + iris { + vddxo-supply = <&pm8921_l4>; + vddrfa-supply = <&pm8921_s2>; + vddpa-supply = <&pm8921_l10>; + vdddig-supply = <&pm8921_lvs2>; + }; +}; + &rpm { regulators { compatible = "qcom,rpm-pm8921-regulators"; -- 2.51.0 From 4b0eb149df58b6750cd8113e5ee5b3ac7cc51743 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 18 Mar 2025 15:21:59 +0200 Subject: [PATCH 11/16] ARM: dts: qcom: apq8064: add missing clocks to the timer node In order to fix DT schema warning and describe hardware properly, add missing sleep clock to the timer node. Fixes: f335b8af4fd5 ("ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410 board device trees") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250318-fix-nexus-4-v2-6-bcedd1406790@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 5f1a6b4b7644..ba99e794dcd2 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -326,6 +326,8 @@ ; reg = <0x0200a000 0x100>; clock-frequency = <27000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; cpu-offset = <0x80000>; }; -- 2.51.0 From 325c6a441ae1f8fcb1db9bb945b8bdbd3142141e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 18 Mar 2025 15:22:00 +0200 Subject: [PATCH 12/16] ARM: dts: qcom: apq8064 merge hw splinlock into corresponding syscon device Follow up the expected way of describing the SFPB hwspinlock and merge hwspinlock node into corresponding syscon node, fixing several dt-schema warnings. Fixes: 24a9baf933dc ("ARM: dts: qcom: apq8064: Add hwmutex and SMEM nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250318-fix-nexus-4-v2-7-bcedd1406790@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index ba99e794dcd2..41f8dcde2081 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -213,12 +213,6 @@ }; }; - sfpb_mutex: hwmutex { - compatible = "qcom,sfpb-mutex"; - syscon = <&sfpb_wrapper_mutex 0x604 0x4>; - #hwlock-cells = <1>; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_region>; @@ -305,9 +299,10 @@ pinctrl-0 = <&ps_hold_default_state>; }; - sfpb_wrapper_mutex: syscon@1200000 { - compatible = "syscon"; - reg = <0x01200000 0x8000>; + sfpb_mutex: hwmutex@1200600 { + compatible = "qcom,sfpb-mutex"; + reg = <0x01200600 0x100>; + #hwlock-cells = <1>; }; intc: interrupt-controller@2000000 { -- 2.51.0 From 2a1282861b73a4b8e45904e079ed3279c3f1c93f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 18 Mar 2025 15:22:01 +0200 Subject: [PATCH 13/16] ARM: dts: qcom: apq8064: use new compatible for SFPB device Use new SoC-specific compatible for the SFPB device node in addition to the "syscon" compatible. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250318-fix-nexus-4-v2-8-bcedd1406790@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 41f8dcde2081..a5aad4f145dd 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -1086,7 +1086,7 @@ }; mmss_sfpb: syscon@5700000 { - compatible = "syscon"; + compatible = "qcom,apq8064-mmss-sfpb", "syscon"; reg = <0x5700000 0x70>; }; -- 2.51.0 From 92c377bcafcddd43d4dca1aa60c865cdd2d1dbbb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 18 Mar 2025 15:22:02 +0200 Subject: [PATCH 14/16] ARM: dts: qcom: apq8064: use new compatible for SPS SIC device Use new SoC-specific compatible to the SPS SIC in addition to the "syscon" compatible and rename the node to follow the purpose of it. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250318-fix-nexus-4-v2-9-bcedd1406790@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index a5aad4f145dd..b6533630e347 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -402,8 +402,8 @@ }; }; - sps_sic_non_secure: sps-sic-non-secure@12100000 { - compatible = "syscon"; + sps_sic_non_secure: interrupt-controller@12100000 { + compatible = "qcom,apq8064-sps-sic", "syscon"; reg = <0x12100000 0x10000>; }; -- 2.51.0 From f2420037d90a8354594b3da541e19dcbb60c75e1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 18 Mar 2025 15:22:03 +0200 Subject: [PATCH 15/16] ARM: dts: qcom: apq8064: move replicator out of soc node The CoreSight static replicator device isn't a part of the system MMIO bus, as such it should not be a part of the soc node. Follow the example of other platforms and move it out of the soc bus to the top-level (and reoder ports to follow alphabetic order). Fixes: 7a5c275fd821 ("ARM: dts: qcom: Add apq8064 CoreSight components") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250318-fix-nexus-4-v2-10-bcedd1406790@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 67 ++++++++++++------------ 1 file changed, 34 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index b6533630e347..b02e6739ccb2 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -278,6 +278,40 @@ }; }; + replicator { + compatible = "arm,coresight-static-replicator"; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&funnel_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -1529,39 +1563,6 @@ }; }; - replicator { - compatible = "arm,coresight-static-replicator"; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&funnel_out>; - }; - }; - }; - }; - funnel@1a04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x1a04000 0x1000>; -- 2.51.0 From b81dcdad43daf10f79ae149826fff9e467b95e8b Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Tue, 18 Mar 2025 22:10:47 -0700 Subject: [PATCH 16/16] ARM: dts: qcom-msm8960: add missing clocks to the timer node In order to fix DT schema warning and describe hardware properly, add missing sleep clock to the timer node. Solved by Dmitry Baryshkov on the APQ8064 SoC Link: https://lore.kernel.org/all/20250318-fix-nexus-4-v2-6-bcedd1406790@oss.qualcomm.com/ Signed-off-by: Rudraksha Gupta Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250318-expressatt-solve-dts-errors-v1-1-14012a4bc315@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index b476ad895119..4babd0bbe5d6 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -154,6 +154,8 @@ ; reg = <0x0200a000 0x100>; clock-frequency = <27000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; cpu-offset = <0x80000>; }; -- 2.51.0