From 08527cb534ff00a8795bf42030e13a8e23391623 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Wed, 29 Jan 2025 00:53:52 +0530 Subject: [PATCH 01/16] drm/amdgpu: Enable devcoredump for JPEG4_0_3 Add register list and enable devcoredump for JPEG4_0_3 V2: (Lijo) - remove version specific callbacks and use simplified helper functions V3: (Lijo) - move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu Acked-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 42 ++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index bc21f12daea8..2a97302a22d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -59,6 +59,42 @@ static int amdgpu_ih_srcid_jpeg[] = { VCN_4_0__SRCID__JPEG7_DECODE }; +static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0_3[] = { + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_SYS_INT_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS), +}; + static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) { return (adev->jpeg.caps & AMDGPU_JPEG_CAPS(RRMT_ENABLED)) == 0; @@ -164,6 +200,10 @@ static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) } } + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0_3, ARRAY_SIZE(jpeg_reg_list_4_0_3)); + if (r) + return r; + /* TODO: Add queue reset mask when FW fully supports it */ adev->jpeg.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); @@ -1066,6 +1106,8 @@ static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { .wait_for_idle = jpeg_v4_0_3_wait_for_idle, .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state, .set_powergating_state = jpeg_v4_0_3_set_powergating_state, + .dump_ip_state = amdgpu_jpeg_dump_ip_state, + .print_ip_state = amdgpu_jpeg_print_ip_state, }; static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { -- 2.51.0 From 358b3774a086b6cc5483781c6ef448b36a7591cb Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Wed, 29 Jan 2025 10:31:32 +0530 Subject: [PATCH 02/16] drm/amdgpu: Enable devcoredump for JPEG5_0_1 Add register list and enable devcoredump for JPEG5_0_1 V2: (Lijo) - remove version specific callbacks and use simplified helper functions V3: (Lijo) - move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu Acked-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 49 ++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h | 61 ++++++++++++++++++++++++ 2 files changed, 108 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index 40d4c32a8c2a..6e3f522e9133 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -52,6 +52,47 @@ static int amdgpu_ih_srcid_jpeg[] = { VCN_5_0__SRCID__JPEG9_DECODE, }; +static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0_1[] = { + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_STATUS), +}; + static int jpeg_v5_0_1_core_reg_offset(u32 pipe) { if (pipe <= AMDGPU_MAX_JPEG_RINGS_4_0_3) @@ -145,6 +186,10 @@ static int jpeg_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) } } + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_1, ARRAY_SIZE(jpeg_reg_list_5_0_1)); + if (r) + return r; + return 0; } @@ -635,8 +680,8 @@ static const struct amd_ip_funcs jpeg_v5_0_1_ip_funcs = { .post_soft_reset = NULL, .set_clockgating_state = jpeg_v5_0_1_set_clockgating_state, .set_powergating_state = jpeg_v5_0_1_set_powergating_state, - .dump_ip_state = NULL, - .print_ip_state = NULL, + .dump_ip_state = amdgpu_jpeg_dump_ip_state, + .print_ip_state = amdgpu_jpeg_print_ip_state, }; static const struct amdgpu_ring_funcs jpeg_v5_0_1_dec_ring_vm_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h index 8ce146c00bb6..9de3272ef47f 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h @@ -26,4 +26,65 @@ extern const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block; +#define regUVD_JRBC0_UVD_JRBC_RB_WPTR 0x0640 +#define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_STATUS 0x0649 +#define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_RB_RPTR 0x064a +#define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_RB_WPTR 0x0000 +#define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC1_UVD_JRBC_STATUS 0x0009 +#define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC1_UVD_JRBC_RB_RPTR 0x000a +#define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC2_UVD_JRBC_RB_WPTR 0x0040 +#define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC2_UVD_JRBC_STATUS 0x0049 +#define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC2_UVD_JRBC_RB_RPTR 0x004a +#define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC3_UVD_JRBC_RB_WPTR 0x0080 +#define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC3_UVD_JRBC_STATUS 0x0089 +#define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC3_UVD_JRBC_RB_RPTR 0x008a +#define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC4_UVD_JRBC_RB_WPTR 0x00c0 +#define regUVD_JRBC4_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC4_UVD_JRBC_STATUS 0x00c9 +#define regUVD_JRBC4_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC4_UVD_JRBC_RB_RPTR 0x00ca +#define regUVD_JRBC4_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC5_UVD_JRBC_RB_WPTR 0x0100 +#define regUVD_JRBC5_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC5_UVD_JRBC_STATUS 0x0109 +#define regUVD_JRBC5_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC5_UVD_JRBC_RB_RPTR 0x010a +#define regUVD_JRBC5_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC6_UVD_JRBC_RB_WPTR 0x0140 +#define regUVD_JRBC6_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC6_UVD_JRBC_STATUS 0x0149 +#define regUVD_JRBC6_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC6_UVD_JRBC_RB_RPTR 0x014a +#define regUVD_JRBC6_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC7_UVD_JRBC_RB_WPTR 0x0180 +#define regUVD_JRBC7_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC7_UVD_JRBC_STATUS 0x0189 +#define regUVD_JRBC7_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC7_UVD_JRBC_RB_RPTR 0x018a +#define regUVD_JRBC7_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC8_UVD_JRBC_RB_WPTR 0x01c0 +#define regUVD_JRBC8_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC8_UVD_JRBC_STATUS 0x01c9 +#define regUVD_JRBC8_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC8_UVD_JRBC_RB_RPTR 0x01ca +#define regUVD_JRBC8_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC9_UVD_JRBC_RB_WPTR 0x0440 +#define regUVD_JRBC9_UVD_JRBC_RB_WPTR_BASE_IDX 1 +#define regUVD_JRBC9_UVD_JRBC_STATUS 0x0449 +#define regUVD_JRBC9_UVD_JRBC_STATUS_BASE_IDX 1 +#define regUVD_JRBC9_UVD_JRBC_RB_RPTR 0x044a +#define regUVD_JRBC9_UVD_JRBC_RB_RPTR_BASE_IDX 1 + #endif /* __JPEG_V5_0_0_H__ */ -- 2.51.0 From c3dddd6029676af390993da980881db9dd26831f Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Wed, 29 Jan 2025 10:46:15 +0530 Subject: [PATCH 03/16] drm/amdgpu: Enable devcoredump for JPEG4_0_0 Add register list and enable devcoredump for JPEG4_0_0 V2: (Lijo) - remove version specific callbacks and use simplified helper functions V3: (Lijo) - move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu Acked-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index 0aef1f64afd0..b0666090f52c 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -36,13 +36,28 @@ #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f +static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0[] = { + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), +}; + static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev); static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev); static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev); static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block, enum amd_powergating_state state); static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev); - static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring); /** @@ -123,6 +138,11 @@ static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block) r = amdgpu_jpeg_ras_sw_init(adev); if (r) return r; + + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0, ARRAY_SIZE(jpeg_reg_list_4_0)); + if (r) + return r; + /* TODO: Add queue reset mask when FW fully supports it */ adev->jpeg.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); @@ -717,6 +737,8 @@ static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { .wait_for_idle = jpeg_v4_0_wait_for_idle, .set_clockgating_state = jpeg_v4_0_set_clockgating_state, .set_powergating_state = jpeg_v4_0_set_powergating_state, + .dump_ip_state = amdgpu_jpeg_dump_ip_state, + .print_ip_state = amdgpu_jpeg_print_ip_state, }; static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { -- 2.51.0 From 2b0ccf3923b5d38672ad801db004580948d7d2c5 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Wed, 29 Jan 2025 10:52:35 +0530 Subject: [PATCH 04/16] drm/amdgpu: Enable devcoredump for JPEG4_0_5 Add register list and enable devcoredump for JPEG4_0_5 V2: (Lijo) - remove version specific callbacks and use simplified helper functions V3: (Lijo) - move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu Acked-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 25 +++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index 6b3656984957..cbba1d9e8367 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -46,11 +46,26 @@ #define regJPEG_CGC_GATE_INTERNAL_OFFSET 0x4160 #define regUVD_NO_OP_INTERNAL_OFFSET 0x0029 +static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0_5[] = { + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), +}; + static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev); static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev); static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block, enum amd_powergating_state state); - static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring); static int amdgpu_ih_clientid_jpeg[] = { @@ -58,6 +73,8 @@ static int amdgpu_ih_clientid_jpeg[] = { SOC15_IH_CLIENTID_VCN1 }; + + /** * jpeg_v4_0_5_early_init - set function pointers * @@ -153,6 +170,10 @@ static int jpeg_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_PITCH); } + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0_5, ARRAY_SIZE(jpeg_reg_list_4_0_5)); + if (r) + return r; + /* TODO: Add queue reset mask when FW fully supports it */ adev->jpeg.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); @@ -759,6 +780,8 @@ static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = { .wait_for_idle = jpeg_v4_0_5_wait_for_idle, .set_clockgating_state = jpeg_v4_0_5_set_clockgating_state, .set_powergating_state = jpeg_v4_0_5_set_powergating_state, + .dump_ip_state = amdgpu_jpeg_dump_ip_state, + .print_ip_state = amdgpu_jpeg_print_ip_state, }; static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = { -- 2.51.0 From d949e91b42f2c18fe8aded0ea002d1b588af2034 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Wed, 29 Jan 2025 12:01:18 +0530 Subject: [PATCH 05/16] drm/amdgpu: Enable devcoredump for JPEG3_0_0 Add register list and enable devcoredump for JPEG3_0_0 V2: (Lijo) - remove version specific callbacks and use simplified helper functions V3: (Lijo) - move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu Acked-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index 4eca65ea9053..a4acb7cb7ea0 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -34,6 +34,22 @@ #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f +static const struct amdgpu_hwip_reg_entry jpeg_reg_list_3_0[] = { + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH), +}; + static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev); static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block, @@ -112,6 +128,10 @@ static int jpeg_v3_0_sw_init(struct amdgpu_ip_block *ip_block) adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_3_0, ARRAY_SIZE(jpeg_reg_list_3_0)); + if (r) + return r; + return 0; } @@ -543,6 +563,8 @@ static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = { .wait_for_idle = jpeg_v3_0_wait_for_idle, .set_clockgating_state = jpeg_v3_0_set_clockgating_state, .set_powergating_state = jpeg_v3_0_set_powergating_state, + .dump_ip_state = amdgpu_jpeg_dump_ip_state, + .print_ip_state = amdgpu_jpeg_print_ip_state, }; static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = { -- 2.51.0 From 63d5f8db53134cfbd085a5d9ed9646451b7647c3 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Wed, 29 Jan 2025 12:08:48 +0530 Subject: [PATCH 06/16] drm/amdgpu: Enable devcoredump for JPEG2_0_0 Add register list and enable devcoredump for JPEG2_0_0 V2: (Lijo) - remove version specific callbacks and use simplified helper functions V3: (Lijo) - move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu Acked-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 7c9251c03815..8c61081746c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -33,6 +33,22 @@ #include "vcn/vcn_2_0_0_sh_mask.h" #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" +static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_0[] = { + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH), +}; + static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev); static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block, @@ -98,6 +114,10 @@ static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block) adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_0, ARRAY_SIZE(jpeg_reg_list_2_0)); + if (r) + return r; + return 0; } @@ -752,6 +772,8 @@ static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = { .wait_for_idle = jpeg_v2_0_wait_for_idle, .set_clockgating_state = jpeg_v2_0_set_clockgating_state, .set_powergating_state = jpeg_v2_0_set_powergating_state, + .dump_ip_state = amdgpu_jpeg_dump_ip_state, + .print_ip_state = amdgpu_jpeg_print_ip_state, }; static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { -- 2.51.0 From 8ecd4ec6a5fddc1ae54cf92dbac0d46131d62fca Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Wed, 29 Jan 2025 12:13:17 +0530 Subject: [PATCH 07/16] drm/amdgpu: Enable devcoredump for JPEG2_5_0 Add register list and enable devcoredump for JPEG2_5_0 V2: (Lijo) - remove version specific callbacks and use simplified helper functions V3: (Lijo) - move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu Acked-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index 11f6af2646e7..b19724928ce4 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -36,6 +36,22 @@ #define JPEG25_MAX_HW_INSTANCES_ARCTURUS 2 +static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_5[] = { + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH), +}; + static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev); static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block, @@ -147,6 +163,10 @@ static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_5, ARRAY_SIZE(jpeg_reg_list_2_5)); + if (r) + return r; + return 0; } @@ -623,6 +643,8 @@ static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = { .wait_for_idle = jpeg_v2_5_wait_for_idle, .set_clockgating_state = jpeg_v2_5_set_clockgating_state, .set_powergating_state = jpeg_v2_5_set_powergating_state, + .dump_ip_state = amdgpu_jpeg_dump_ip_state, + .print_ip_state = amdgpu_jpeg_print_ip_state, }; static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = { @@ -638,6 +660,8 @@ static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = { .wait_for_idle = jpeg_v2_5_wait_for_idle, .set_clockgating_state = jpeg_v2_5_set_clockgating_state, .set_powergating_state = jpeg_v2_5_set_powergating_state, + .dump_ip_state = amdgpu_jpeg_dump_ip_state, + .print_ip_state = amdgpu_jpeg_print_ip_state, }; static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { -- 2.51.0 From 64dc2f0029ec42abaf87c44c636b12dff32ea395 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Thu, 30 Jan 2025 12:35:42 +0530 Subject: [PATCH 08/16] drm/amdgpu: Enable devcoredump for JPEG5_0_0 Add register list and enable devcoredump for JPEG5_0_0 V2: (Lijo) - remove version specific callbacks and use simplified helper functions V3: (Lijo) - move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu Acked-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index d5cf0f2799d4..4a55e0cf39e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -34,6 +34,22 @@ #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" #include "jpeg_v5_0_0.h" +static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0[] = { + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), +}; + static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev); static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev); static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block, @@ -100,6 +116,10 @@ static int jpeg_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0, ARRAY_SIZE(jpeg_reg_list_5_0)); + if (r) + return r; + /* TODO: Add queue reset mask when FW fully supports it */ adev->jpeg.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); @@ -637,6 +657,8 @@ static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = { .wait_for_idle = jpeg_v5_0_0_wait_for_idle, .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state, .set_powergating_state = jpeg_v5_0_0_set_powergating_state, + .dump_ip_state = amdgpu_jpeg_dump_ip_state, + .print_ip_state = amdgpu_jpeg_print_ip_state, }; static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = { -- 2.51.0 From 568199a5c7a971c5571a40f925938acbb48ad329 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 31 Jan 2025 18:16:12 +0530 Subject: [PATCH 09/16] drm/amd/pm: Limit to 8 jpeg rings per instance JPEG 5.0.1 supports upto 10 rings, however PMFW support for SMU v13.0.6 variants is now limited to 8 per instance. Limit to 8 temporarily to avoid out of bounds access. Signed-off-by: Lijo Lazar Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index dc839f9a2295..d645387beaa4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -2507,6 +2507,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table MetricsTableV2_t *metrics_v2; struct amdgpu_xcp *xcp; u16 link_width_level; + u8 num_jpeg_rings; u32 inst_mask; bool per_inst; @@ -2643,6 +2644,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS)); + num_jpeg_rings = max_t(u8, adev->jpeg.num_jpeg_rings, 8); for_each_xcp(adev->xcp_mgr, xcp, i) { amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); idx = 0; @@ -2650,11 +2652,11 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table /* Both JPEG and VCN has same instances */ inst = GET_INST(VCN, k); - for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + for (j = 0; j < num_jpeg_rings; ++j) { gpu_metrics->xcp_stats[i].jpeg_busy - [(idx * adev->jpeg.num_jpeg_rings) + j] = + [(idx * num_jpeg_rings) + j] = SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, version) - [(inst * adev->jpeg.num_jpeg_rings) + j]); + [(inst * num_jpeg_rings) + j]); } gpu_metrics->xcp_stats[i].vcn_busy[idx] = SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]); -- 2.51.0 From 3bd202b3c4c7235499060ead7b3a4ffe7008a8aa Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Sun, 2 Feb 2025 21:58:50 +0000 Subject: [PATCH 10/16] drm/amd/display: Remove unused mpc1_is_mpcc_idle mpc1_is_mpcc_idle() was added in 2017 by commit feb4a3cd8eb0 ("drm/amd/display: Integrating MPC pseudocode") but never used. Remove it. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c | 16 ---------------- .../gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h | 4 ---- 2 files changed, 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c index f2f55565e98a..b23c64004dd5 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c @@ -142,22 +142,6 @@ struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) return NULL; } -bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id) -{ - struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - unsigned int top_sel; - unsigned int opp_id; - unsigned int idle; - - REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); - REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); - REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); - if (top_sel == 0xf && opp_id == 0xf && idle) - return true; - else - return false; -} - void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) { struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h index dbfffc6383dc..874e36e39e1b 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h @@ -173,10 +173,6 @@ void mpc1_update_stereo_mix( struct mpcc_sm_cfg *sm_cfg, int mpcc_id); -bool mpc1_is_mpcc_idle( - struct mpc *mpc, - int mpcc_id); - void mpc1_assert_mpcc_idle_before_connect( struct mpc *mpc, int mpcc_id); -- 2.51.0 From 2d5e8a8997aa3ca153fc2ad016c88012c97afa9e Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Sun, 2 Feb 2025 21:58:51 +0000 Subject: [PATCH 11/16] drm/amd/display: Remove unused freesync functions mod_freesync_get_vmin_vmax() and mod_freesync_get_v_position() were added in 2017 by commit 72ada5f76939 ("drm/amd/display: FreeSync Auto Sweep Support") mod_freesync_is_valid_range() was added in 2018 by commit e80e94460841 ("drm/amd/display: add method to check for supported range") mod_freesync_get_settings() was added in 2018 by commit a3e1737ed61c ("drm/amd/display: Implement stats logging") and mod_freesync_calc_field_rate_from_timing() was added in 2020 by commit 49c70ece54b0 ("drm/amd/display: Change input parameter for set_drr") None of these have been used. Remove them. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- .../amd/display/modules/freesync/freesync.c | 137 ------------------ .../amd/display/modules/inc/mod_freesync.h | 26 ---- 2 files changed, 163 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 2b3964529539..3ba9b62ba70b 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -552,43 +552,6 @@ static bool vrr_settings_require_update(struct core_freesync *core_freesync, return false; } -bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - const struct dc_stream_state *stream, - unsigned int *vmin, - unsigned int *vmax) -{ - *vmin = stream->adjust.v_total_min; - *vmax = stream->adjust.v_total_max; - - return true; -} - -bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - struct dc_stream_state *stream, - unsigned int *nom_v_pos, - unsigned int *v_pos) -{ - struct core_freesync *core_freesync = NULL; - struct crtc_position position; - - if (mod_freesync == NULL) - return false; - - core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - - if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1, - &position.vertical_count, - &position.nominal_vcount)) { - - *nom_v_pos = position.nominal_vcount; - *v_pos = position.vertical_count; - - return true; - } - - return false; -} - static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr, struct dc_info_packet *infopacket, bool freesync_on_desktop) @@ -1291,28 +1254,6 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, } } -void mod_freesync_get_settings(struct mod_freesync *mod_freesync, - const struct mod_vrr_params *vrr, - unsigned int *v_total_min, unsigned int *v_total_max, - unsigned int *event_triggers, - unsigned int *window_min, unsigned int *window_max, - unsigned int *lfc_mid_point_in_us, - unsigned int *inserted_frames, - unsigned int *inserted_duration_in_us) -{ - if (mod_freesync == NULL) - return; - - if (vrr->supported) { - *v_total_min = vrr->adjust.v_total_min; - *v_total_max = vrr->adjust.v_total_max; - *event_triggers = 0; - *lfc_mid_point_in_us = vrr->btr.mid_point_in_us; - *inserted_frames = vrr->btr.frames_to_insert; - *inserted_duration_in_us = vrr->btr.inserted_duration_in_us; - } -} - unsigned long long mod_freesync_calc_nominal_field_rate( const struct dc_stream_state *stream) { @@ -1328,85 +1269,7 @@ unsigned long long mod_freesync_calc_nominal_field_rate( return nominal_field_rate_in_uhz; } -unsigned long long mod_freesync_calc_field_rate_from_timing( - unsigned int vtotal, unsigned int htotal, unsigned int pix_clk) -{ - unsigned long long field_rate_in_uhz = 0; - unsigned int total = htotal * vtotal; - - /* Calculate nominal field rate for stream, rounded up to nearest integer */ - field_rate_in_uhz = pix_clk; - field_rate_in_uhz *= 1000000ULL; - - field_rate_in_uhz = div_u64(field_rate_in_uhz, total); - - return field_rate_in_uhz; -} - bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr) { return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED); } - -bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz, - uint32_t max_refresh_cap_in_uhz, - uint32_t nominal_field_rate_in_uhz) -{ - - /* Typically nominal refresh calculated can have some fractional part. - * Allow for some rounding error of actual video timing by taking floor - * of caps and request. Round the nominal refresh rate. - * - * Dividing will convert everything to units in Hz although input - * variable name is in uHz! - * - * Also note, this takes care of rounding error on the nominal refresh - * so by rounding error we only expect it to be off by a small amount, - * such as < 0.1 Hz. i.e. 143.9xxx or 144.1xxx. - * - * Example 1. Caps Min = 40 Hz, Max = 144 Hz - * Request Min = 40 Hz, Max = 144 Hz - * Nominal = 143.5x Hz rounded to 144 Hz - * This function should allow this as valid request - * - * Example 2. Caps Min = 40 Hz, Max = 144 Hz - * Request Min = 40 Hz, Max = 144 Hz - * Nominal = 144.4x Hz rounded to 144 Hz - * This function should allow this as valid request - * - * Example 3. Caps Min = 40 Hz, Max = 144 Hz - * Request Min = 40 Hz, Max = 144 Hz - * Nominal = 120.xx Hz rounded to 120 Hz - * This function should return NOT valid since the requested - * max is greater than current timing's nominal - * - * Example 4. Caps Min = 40 Hz, Max = 120 Hz - * Request Min = 40 Hz, Max = 120 Hz - * Nominal = 144.xx Hz rounded to 144 Hz - * This function should return NOT valid since the nominal - * is greater than the capability's max refresh - */ - nominal_field_rate_in_uhz = - div_u64(nominal_field_rate_in_uhz + 500000, 1000000); - min_refresh_cap_in_uhz /= 1000000; - max_refresh_cap_in_uhz /= 1000000; - - /* Check nominal is within range */ - if (nominal_field_rate_in_uhz > max_refresh_cap_in_uhz || - nominal_field_rate_in_uhz < min_refresh_cap_in_uhz) - return false; - - /* If nominal is less than max, limit the max allowed refresh rate */ - if (nominal_field_rate_in_uhz < max_refresh_cap_in_uhz) - max_refresh_cap_in_uhz = nominal_field_rate_in_uhz; - - /* Check min is within range */ - if (min_refresh_cap_in_uhz > max_refresh_cap_in_uhz) - return false; - - /* For variable range, check for at least 10 Hz range */ - if (nominal_field_rate_in_uhz - min_refresh_cap_in_uhz < 10) - return false; - - return true; -} diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index cc3dc9b589f6..57916ed98c86 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -110,25 +110,6 @@ struct mod_vrr_params { struct mod_freesync *mod_freesync_create(struct dc *dc); void mod_freesync_destroy(struct mod_freesync *mod_freesync); -bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - const struct dc_stream_state *stream, - unsigned int *vmin, - unsigned int *vmax); - -bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - struct dc_stream_state *stream, - unsigned int *nom_v_pos, - unsigned int *v_pos); - -void mod_freesync_get_settings(struct mod_freesync *mod_freesync, - const struct mod_vrr_params *vrr, - unsigned int *v_total_min, unsigned int *v_total_max, - unsigned int *event_triggers, - unsigned int *window_min, unsigned int *window_max, - unsigned int *lfc_mid_point_in_us, - unsigned int *inserted_frames, - unsigned int *inserted_duration_in_us); - void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, const struct dc_stream_state *stream, const struct mod_vrr_params *vrr, @@ -155,13 +136,6 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, unsigned long long mod_freesync_calc_nominal_field_rate( const struct dc_stream_state *stream); -unsigned long long mod_freesync_calc_field_rate_from_timing( - unsigned int vtotal, unsigned int htotal, unsigned int pix_clk); - -bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz, - uint32_t max_refresh_cap_in_uhz, - uint32_t nominal_field_rate_in_uhz); - unsigned int mod_freesync_calc_v_total_from_refresh( const struct dc_stream_state *stream, unsigned int refresh_in_uhz); -- 2.51.0 From fa88342931bad919a542ae4348bfd4ef0afaf5ca Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Sun, 2 Feb 2025 21:58:52 +0000 Subject: [PATCH 12/16] drm/amd/display: Remove unused dc_stream_get_crtc_position The last user of dc_stream_get_crtc_position() was mod_freesync_get_v_position() which is removed in a previous patch in this series. Remove it. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 27 ---------------------- drivers/gpu/drm/amd/display/dc/dc_stream.h | 12 ---------- 2 files changed, 39 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a2b0331ef579..e204b69fbc18 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -516,33 +516,6 @@ bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, return status; } -bool dc_stream_get_crtc_position(struct dc *dc, - struct dc_stream_state **streams, int num_streams, - unsigned int *v_pos, unsigned int *nom_v_pos) -{ - /* TODO: Support multiple streams */ - const struct dc_stream_state *stream = streams[0]; - int i; - bool ret = false; - struct crtc_position position; - - dc_exit_ips_for_hw_access(dc); - - for (i = 0; i < MAX_PIPES; i++) { - struct pipe_ctx *pipe = - &dc->current_state->res_ctx.pipe_ctx[i]; - - if (pipe->stream == stream && pipe->stream_res.stream_enc) { - dc->hwss.get_position(&pipe, 1, &position); - - *v_pos = position.vertical_count; - *nom_v_pos = position.nominal_vcount; - ret = true; - } - } - return ret; -} - #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) static inline void dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv, diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 3e303c7808fb..e0bfddaa23e3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -528,12 +528,6 @@ bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, struct dc_stream_state *stream, uint32_t *refresh_rate); -bool dc_stream_get_crtc_position(struct dc *dc, - struct dc_stream_state **stream, - int num_streams, - unsigned int *v_pos, - unsigned int *nom_v_pos); - #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) bool dc_stream_forward_crc_window(struct dc_stream_state *stream, struct rect *rect, @@ -578,12 +572,6 @@ bool dc_stream_set_gamut_remap(struct dc *dc, bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream); -bool dc_stream_get_crtc_position(struct dc *dc, - struct dc_stream_state **stream, - int num_streams, - unsigned int *v_pos, - unsigned int *nom_v_pos); - struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream); void dc_dmub_update_dirty_rect(struct dc *dc, -- 2.51.0 From 6d04e9785cd153f17a34ecb1d3ac7d848ca4339a Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Sun, 2 Feb 2025 21:58:53 +0000 Subject: [PATCH 13/16] drm/amd/display: Remove unused get_clock_requirements_for_state get_clock_requirements_for_state() was added in 2018 by commit 8ab2180f96f5 ("drm/amd/display: Add function to fetch clock requirements") but never used. Remove it. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ------------ drivers/gpu/drm/amd/display/dc/dc.h | 2 -- 2 files changed, 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e204b69fbc18..c5f1b61ed640 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5449,18 +5449,6 @@ bool dc_is_dmcu_initialized(struct dc *dc) return false; } -void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info) -{ - info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz; - info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz; - info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz; - info->maxSupportedDppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; - info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz; - info->socClock = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz; - info->dcfClockDeepSleep = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz; - info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz; - info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz; -} enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping) { if (dc->hwss.set_clock) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e5e4cb3d0a0d..42ba65e785ca 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1582,8 +1582,6 @@ bool dc_validate_boot_timing(const struct dc *dc, enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); -void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); - enum dc_status dc_validate_with_context(struct dc *dc, const struct dc_validation_set set[], int set_count, -- 2.51.0 From 9ab737f3aeea29129903de6ddebf4bbce3ec0644 Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Sun, 2 Feb 2025 21:58:54 +0000 Subject: [PATCH 14/16] drm/amd/display: Remove unused hubbub1_toggle_watermark_change_req hubbub1_toggle_watermark_change_req() last use was removed in 2017 by commit b8fce2c9d773 ("drm/amd/display: Optimize programming front end") Remove it. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- .../amd/display/dc/hubbub/dcn10/dcn10_hubbub.c | 18 ------------------ .../amd/display/dc/hubbub/dcn10/dcn10_hubbub.h | 3 --- 2 files changed, 21 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c index d738a36f2132..7847c1c4927b 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c @@ -679,24 +679,6 @@ void hubbub1_update_dchub( dh_data->dchub_info_valid = false; } -void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - - uint32_t watermark_change_req; - - REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req); - - if (watermark_change_req) - watermark_change_req = 0; - else - watermark_change_req = 1; - - REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); -} - void hubbub1_soft_reset(struct hubbub *hubbub, bool reset) { struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h index 9fbd45c7dfef..fa5c4c18ed59 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h @@ -489,9 +489,6 @@ void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow); bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub); -void hubbub1_toggle_watermark_change_req( - struct hubbub *hubbub); - void hubbub1_wm_read_state(struct hubbub *hubbub, struct dcn_hubbub_wm *wm); -- 2.51.0 From 6d4e03d0b1ba9cfc75a600519a15f41c2e7e5a6d Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Sun, 2 Feb 2025 21:58:55 +0000 Subject: [PATCH 15/16] drm/amd/display: Remove unused get_max_support_fbc_buffersize get_max_support_fbc_buffersize() is unused since 2021's commit 94f0d0c80cf3 ("drm/amd/display/dc/dce110/dce110_compressor: Remove unused function 'dce110_get_required_compressed_surfacesize") removed it's only caller. Remove it. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce110/dce110_compressor.c | 13 ------------- .../drm/amd/display/dc/dce110/dce110_compressor.h | 2 -- 2 files changed, 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index d241ee13b293..59a0961b49da 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -409,19 +409,6 @@ void dce110_compressor_destroy(struct compressor **compressor) *compressor = NULL; } -void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y) -{ - *max_x = FBC_MAX_X; - *max_y = FBC_MAX_Y; - - /* if (m_smallLocalFrameBufferMemory == 1) - * { - * *max_x = FBC_MAX_X_SG; - * *max_y = FBC_MAX_Y_SG; - * } - */ -} - static const struct compressor_funcs dce110_compressor_funcs = { .power_up_fbc = dce110_compressor_power_up_fbc, .enable_fbc = dce110_compressor_enable_fbc, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h index 26c7335a1cbf..223c57941e92 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h @@ -75,7 +75,5 @@ void dce110_compressor_program_lpt_control(struct compressor *cp, bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *cp); -void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y); - #endif -- 2.51.0 From b0fce908cf5db7d624c83f81050211e158febabd Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Sun, 2 Feb 2025 21:58:56 +0000 Subject: [PATCH 16/16] drm/amd/display: Remove unused link_enc_cfg_get_link_enc_used_by_stream link_enc_cfg_get_link_enc_used_by_stream() is no longer used after 2021's: commit 6366b00346c0 ("drm/amd/display: Maintain consistent mode of operation during encoder assignment") which introduces and uses the _current version instead. Remove it. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 11 ----------- drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 5 ----- 2 files changed, 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c index 039b176e086d..08b4258b0e2f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c @@ -559,17 +559,6 @@ struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc) return link_enc; } -struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream( - struct dc *dc, - const struct dc_stream_state *stream) -{ - struct link_encoder *link_enc; - - link_enc = link_enc_cfg_get_link_enc_used_by_link(dc, stream->link); - - return link_enc; -} - struct link_encoder *link_enc_cfg_get_link_enc( const struct dc_link *link) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h index dc650be3837e..f1afb31ac70b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h @@ -96,11 +96,6 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_link( /* Return next available DIG link encoder. NULL if none available. */ struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc); -/* Return DIG link encoder used by stream. NULL if unused. */ -struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream( - struct dc *dc, - const struct dc_stream_state *stream); - /* Return DIG link encoder. NULL if unused. */ struct link_encoder *link_enc_cfg_get_link_enc(const struct dc_link *link); -- 2.51.0