From 7185c9cd0e2281b113dacbf3c160ffcce06c912d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 27 Mar 2025 02:47:07 +0100 Subject: [PATCH 01/16] arm64: dts: qcom: qcs615: Remove disallowed property from AOSS_QMP node AOSS_QMP is not allowed to be a power domain provider, remove the associated -cells property. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250327-topic-more_dt_bindings_fixes-v2-5-b763d958545f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index f08ba09772f3..3e2d312be88c 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3238,7 +3238,6 @@ mboxes = <&apss_shared 0>; #clock-cells = <0>; - #power-domain-cells = <1>; }; sram@c3f0000 { -- 2.51.0 From bd0eaca2f1be0ea72b7e0b9433c6102c47b28eed Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 27 Mar 2025 02:47:08 +0100 Subject: [PATCH 02/16] arm64: dts: qcom: msm8998-fxtec: Add QUSB2PHY VDD supply Set the supply as required by bindings, to silence the warning: 'vdd-supply' is a required property The value is inferred from MTP schematics, but it shouldn't change between boards due to specific electrical characteristics. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250327-topic-more_dt_bindings_fixes-v2-6-b763d958545f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index f1ceaedd9520..f5558495cb02 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -372,6 +372,7 @@ &qusb2phy { status = "okay"; + vdd-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; -- 2.51.0 From 3e060720fa26cb5262f16ed60022c0f816be56fd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 27 Mar 2025 02:47:09 +0100 Subject: [PATCH 03/16] arm64: dts: qcom: msm8998-mtp: Add QUSB2PHY VDD supply Set the supply as required by bindings, to silence the warning: 'vdd-supply' is a required property Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250327-topic-more_dt_bindings_fixes-v2-7-b763d958545f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998-mtp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts index 7c77612fb990..ad425267e902 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts @@ -156,6 +156,7 @@ &qusb2phy { status = "okay"; + vdd-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; -- 2.51.0 From b108ca47ea14068ca38cf9129d3592dc4ee79e5d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 27 Mar 2025 02:47:10 +0100 Subject: [PATCH 04/16] arm64: dts: qcom: msm8998-yoshino: Add QUSB2PHY VDD supply Set the supply as required by bindings, to silence the warning: 'vdd-supply' is a required property The value is inferred from MTP schematics, but it shouldn't change between boards due to specific electrical characteristics. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250327-topic-more_dt_bindings_fixes-v2-8-b763d958545f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index d8cc0d729e99..3650f2501886 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -450,6 +450,7 @@ &qusb2phy { status = "okay"; + vdd-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; -- 2.51.0 From a30e5b31751ca8a5d5f79f10b594926ac094965d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 27 Mar 2025 02:47:11 +0100 Subject: [PATCH 05/16] arm64: dts: qcom: sm6350-pdx213: Wire up USB regulators Wire up the regulators based on the downstream release to appease the devicetree checker. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250327-topic-more_dt_bindings_fixes-v2-9-b763d958545f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index bf23033a294e..8848043f95f2 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -381,9 +381,16 @@ }; &usb_1_hsphy { + vdd-supply = <&pm6350_l18>; + vdda-phy-dpdm-supply = <&pm6350_l3>; + vdda-pll-supply = <&pm6350_l2>; + status = "okay"; }; &usb_1_qmpphy { + vdda-phy-supply = <&pm6350_l16>; + vdda-pll-supply = <&pm6350_l22>; + status = "okay"; }; -- 2.51.0 From 27880745470afe3ad97967c4751a1ecdb5d245ce Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 27 Mar 2025 02:47:12 +0100 Subject: [PATCH 06/16] arm64: dts: qcom: msm8996-oneplus: Add SLPI VDD_PX The PX line powers some hardware related to sensors. Assume the board doesn't reinvent what MTP has established and hook up LVS2 @ 1.8V as such. This fixes the 'is required' type of bindings validator errors. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250327-topic-more_dt_bindings_fixes-v2-10-b763d958545f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi | 5 +++++ arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts | 2 ++ 3 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 3897a177f12e..63ab564655bc 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -492,6 +492,11 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + vreg_lvs2a: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts index dfe75119b8d2..220eeb31fdc7 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts @@ -41,6 +41,8 @@ &slpi_pil { firmware-name = "qcom/msm8996/oneplus3/slpi.mbn"; + px-supply = <&vreg_lvs2a>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts index 51fce65e89f1..f772618e80c7 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts @@ -42,6 +42,8 @@ &slpi_pil { firmware-name = "qcom/msm8996/oneplus3t/slpi.mbn"; + px-supply = <&vreg_lvs2a>; + status = "okay"; }; -- 2.51.0 From f275447923600ba463133ae5c15c079bccf6b5a6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 27 Mar 2025 02:47:13 +0100 Subject: [PATCH 07/16] arm64: dts: qcom: sa8775p: Clean up the PSCI PDs Because SA8775P comes with two disjoint CPU clusters, we have to follow a similar topology description like the one in sm8750.dtsi, so: system_pd cluster0_pd cpu_pd0 ... cluster1_pd cpu_pd4 ... Do that & wire it up to APPS RSC to make the bindings checker happy. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250327-topic-more_dt_bindings_fixes-v2-11-b763d958545f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 3261c243940c..45f536633f64 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -471,17 +471,17 @@ cluster_0_pd: power-domain-cluster0 { #power-domain-cells = <0>; - power-domains = <&cluster_2_pd>; domain-idle-states = <&cluster_sleep_gold>; + power-domains = <&system_pd>; }; cluster_1_pd: power-domain-cluster1 { #power-domain-cells = <0>; - power-domains = <&cluster_2_pd>; domain-idle-states = <&cluster_sleep_gold>; + power-domains = <&system_pd>; }; - cluster_2_pd: power-domain-cluster2 { + system_pd: power-domain-system { #power-domain-cells = <0>; domain-idle-states = <&cluster_sleep_apss_rsc_pc>; }; @@ -5484,6 +5484,7 @@ , ; label = "apps_rsc"; + power-domains = <&system_pd>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; -- 2.51.0 From ea172f61f4fdb17aaaf8def980ee309a3b727eea Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 27 Mar 2025 02:47:14 +0100 Subject: [PATCH 08/16] arm64: dts: qcom: qcs615: Fix up UFS clocks The clocks are out of order with the bindings' expectations. Reorder them to resolve the errors. Fixes: a6a9d10e7969 ("arm64: dts: qcom: qcs615: add UFS node") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250327-topic-more_dt_bindings_fixes-v2-12-b763d958545f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 3e2d312be88c..bb8b6c3ebd03 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -1033,10 +1033,10 @@ "bus_aggr_clk", "iface_clk", "core_clk_unipro", - "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", - "rx_lane0_sync_clk"; + "rx_lane0_sync_clk", + "ice_core_clk"; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; @@ -1071,10 +1071,10 @@ /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <37500000>, - /bits/ 64 <75000000>, /bits/ 64 <0>, /bits/ 64 <0>, - /bits/ 64 <0>; + /bits/ 64 <0>, + /bits/ 64 <75000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -1083,10 +1083,10 @@ /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <75000000>, - /bits/ 64 <150000000>, /bits/ 64 <0>, /bits/ 64 <0>, - /bits/ 64 <0>; + /bits/ 64 <0>, + /bits/ 64 <150000000>; required-opps = <&rpmhpd_opp_svs>; }; @@ -1095,10 +1095,10 @@ /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <150000000>, - /bits/ 64 <300000000>, /bits/ 64 <0>, /bits/ 64 <0>, - /bits/ 64 <0>; + /bits/ 64 <0>, + /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_nom>; }; }; -- 2.51.0 From 435c3642a6a82c774f2897d72e6ed794a1dbaba1 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Fri, 28 Mar 2025 15:58:29 +0530 Subject: [PATCH 09/16] arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data rates used in lane equalization procedure. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20250328-preset_v6-v9-1-22cfa0490518@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 2577a0f4dd71..1f0e50b0e6a1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3225,6 +3225,10 @@ phys = <&pcie3_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + operating-points-v2 = <&pcie3_opp_table>; status = "disabled"; @@ -3427,6 +3431,9 @@ phys = <&pcie6a_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + status = "disabled"; }; @@ -3554,6 +3561,8 @@ phys = <&pcie5_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; }; @@ -3680,6 +3689,8 @@ phys = <&pcie4_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; pcie4_port0: pcie@0 { -- 2.51.0 From fff7f1c8442b2b2be565892b0d42bb9ef9723fb3 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Fri, 28 Mar 2025 19:46:45 +0100 Subject: [PATCH 10/16] arm64: dts: qcom: x1e80100-vivobook-s15: Add bluetooth Add bluetooth for the asus vivobook s15 Describe wlan configuration Reviewed-by: Dmitry Baryshkov Acked-by: Konrad Dybcio Signed-off-by: Maud Spierings Link: https://lore.kernel.org/r/20250328-asus_qcom_display-v7-1-322d2bff937d@hotmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/x1e80100-asus-vivobook-s15.dts | 167 ++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index a9ac4b81daf6..71b2cc6c392f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -19,6 +19,10 @@ compatible = "asus,vivobook-s15", "qcom,x1e80100"; chassis-type = "laptop"; + aliases { + serial1 = &uart14; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&hall_int_n_default>; @@ -153,6 +157,107 @@ regulator-always-on; regulator-boot-on; }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_en>, <&wcn_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -212,6 +317,13 @@ regulator-max-microvolt = <3072000>; regulator-initial-mode = ; }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; }; regulators-1 { @@ -538,6 +650,23 @@ status = "okay"; }; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie6a { perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; @@ -719,6 +848,44 @@ function = "gpio"; bias-disable; }; + + wcn_bt_en: wcn-bt-en-state { + pins = "gpio116"; + function = "gpio"; + drive-strength = <16>; + bias-pull-down; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + wcn_wlan_en: wcn-wlan-en-state { + pins = "gpio117"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; }; &usb_1_ss0_hsphy { -- 2.51.0 From 831e7dcc06cd3eff2213c691413e4bd0550ddcdf Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Mon, 31 Mar 2025 14:36:41 +0200 Subject: [PATCH 11/16] arm64: dts: qcom: qcm2290: Add crypto engine Add Qualcomm Crypto Engine (QCE) and BAM related nodes for this SoC. Signed-off-by: Loic Poulain Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250331123641.1590573-1-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index c7946731438b..f49ac1c1f8a3 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -757,6 +757,30 @@ #interconnect-cells = <2>; }; + cryptobam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x01b04000 0x0 0x24000>; + interrupts = ; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x0084 0x11>, + <&apps_smmu 0x0086 0x11>; + }; + + crypto: crypto@1b3a000 { + compatible = "qcom,qcm2290-qce", "qcom,ipq4019-qce", "qcom,qce"; + reg = <0x0 0x01b3a000 0x0 0x6000>; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x0084 0x11>, + <&apps_smmu 0x0086 0x11>; + }; + qfprom@1b44000 { compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; reg = <0x0 0x01b44000 0x0 0x3000>; -- 2.51.0 From 5cf0ebd4800dc5b67a332c9f56d20882c41d6099 Mon Sep 17 00:00:00 2001 From: Kaushal Kumar Date: Tue, 15 Apr 2025 12:57:54 +0530 Subject: [PATCH 12/16] arm64: dts: qcom: sdx75: Add QPIC BAM support Add devicetree node to enable support for QPIC BAM DMA controller on Qualcomm SDX75 platform. Signed-off-by: Kaushal Kumar Link: https://lore.kernel.org/r/20250415072756.20046-4-quic_kaushalk@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 8e63f635a327..9b89ed6d1181 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -880,6 +880,20 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + qpic_bam: dma-controller@1c9c000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x01c9c000 0x0 0x1c000>; + interrupts = ; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x100 0x3>; + dma-coherent; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; -- 2.51.0 From c25dcb4d42a9506d5270179bb32cf538a1a28423 Mon Sep 17 00:00:00 2001 From: Kaushal Kumar Date: Tue, 15 Apr 2025 12:57:55 +0530 Subject: [PATCH 13/16] arm64: dts: qcom: sdx75: Add QPIC NAND support Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX75 platform. Signed-off-by: Kaushal Kumar Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415072756.20046-5-quic_kaushalk@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 9b89ed6d1181..75bfc19f412c 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -894,6 +894,25 @@ status = "disabled"; }; + qpic_nand: nand-controller@1cc8000 { + compatible = "qcom,sdx75-nand", "qcom,sdx55-nand"; + reg = <0x0 0x01cc8000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&sleep_clk>; + clock-names = "core", + "aon"; + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", + "rx", + "cmd"; + iommus = <&apps_smmu 0x100 0x3>; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; -- 2.51.0 From d838ac6903eede0c2840bebd8788afa95a5aa0fb Mon Sep 17 00:00:00 2001 From: Kaushal Kumar Date: Tue, 15 Apr 2025 12:57:56 +0530 Subject: [PATCH 14/16] arm64: dts: qcom: sdx75-idp: Enable QPIC BAM & QPIC NAND support Enable QPIC BAM and QPIC NAND devicetree nodes for Qualcomm SDX75-IDP board. Signed-off-by: Kaushal Kumar Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415072756.20046-6-quic_kaushalk@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75-idp.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts index f1bbe7ab01ab..06cacec3461f 100644 --- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -278,6 +278,24 @@ vdd3-supply = <&vreg_l10b_3p08>; }; +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + /* efs2 partition is secured */ + secure-regions = /bits/ 64 <0x680000 0xb00000>; + }; +}; + &qupv3_id_0 { status = "okay"; }; -- 2.51.0 From 2a49326081e1e5f08e0e6d65a1632652ee11a319 Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Wed, 16 Apr 2025 18:54:18 +0800 Subject: [PATCH 15/16] arm64: dts: qcom: sc7280: Mark FastRPC context banks as dma-coherent The FastRPC context banks are DMA-coherent on sc7280 platform. Mark them as such. This allows LLM inferencing on the CDSP using Qualcomm AI Engine Direct SDK on the qcs6490 platform. Signed-off-by: Xilin Wu Link: https://lore.kernel.org/r/20250416-sc7280-fastrpc-dma-v1-1-60ca91116b1e@radxa.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ac59dd41a495..b1cc3bc1aec8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3906,18 +3906,21 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x1803 0x0>; + dma-coherent; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x1804 0x0>; + dma-coherent; }; compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x1805 0x0>; + dma-coherent; }; }; }; @@ -4145,6 +4148,7 @@ reg = <1>; iommus = <&apps_smmu 0x11a1 0x0420>, <&apps_smmu 0x1181 0x0420>; + dma-coherent; }; compute-cb@2 { @@ -4152,6 +4156,7 @@ reg = <2>; iommus = <&apps_smmu 0x11a2 0x0420>, <&apps_smmu 0x1182 0x0420>; + dma-coherent; }; compute-cb@3 { @@ -4159,6 +4164,7 @@ reg = <3>; iommus = <&apps_smmu 0x11a3 0x0420>, <&apps_smmu 0x1183 0x0420>; + dma-coherent; }; compute-cb@4 { @@ -4166,6 +4172,7 @@ reg = <4>; iommus = <&apps_smmu 0x11a4 0x0420>, <&apps_smmu 0x1184 0x0420>; + dma-coherent; }; compute-cb@5 { @@ -4173,6 +4180,7 @@ reg = <5>; iommus = <&apps_smmu 0x11a5 0x0420>, <&apps_smmu 0x1185 0x0420>; + dma-coherent; }; compute-cb@6 { @@ -4180,6 +4188,7 @@ reg = <6>; iommus = <&apps_smmu 0x11a6 0x0420>, <&apps_smmu 0x1186 0x0420>; + dma-coherent; }; compute-cb@7 { @@ -4187,6 +4196,7 @@ reg = <7>; iommus = <&apps_smmu 0x11a7 0x0420>, <&apps_smmu 0x1187 0x0420>; + dma-coherent; }; compute-cb@8 { @@ -4194,6 +4204,7 @@ reg = <8>; iommus = <&apps_smmu 0x11a8 0x0420>, <&apps_smmu 0x1188 0x0420>; + dma-coherent; }; /* note: secure cb9 in downstream */ @@ -4203,6 +4214,7 @@ reg = <11>; iommus = <&apps_smmu 0x11ab 0x0420>, <&apps_smmu 0x118b 0x0420>; + dma-coherent; }; compute-cb@12 { @@ -4210,6 +4222,7 @@ reg = <12>; iommus = <&apps_smmu 0x11ac 0x0420>, <&apps_smmu 0x118c 0x0420>; + dma-coherent; }; compute-cb@13 { @@ -4217,6 +4230,7 @@ reg = <13>; iommus = <&apps_smmu 0x11ad 0x0420>, <&apps_smmu 0x118d 0x0420>; + dma-coherent; }; compute-cb@14 { @@ -4224,6 +4238,7 @@ reg = <14>; iommus = <&apps_smmu 0x11ae 0x0420>, <&apps_smmu 0x118e 0x0420>; + dma-coherent; }; }; }; -- 2.51.0 From ab7f31a3830d7ab2cbc8e4be56c424e66adc5dbe Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Wed, 16 Apr 2025 17:55:37 +0530 Subject: [PATCH 16/16] arm64: dts: qcom: ipq5424: Add PCIe PHYs and controller nodes Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices found on IPQ5424 platform. The PCIe0 & PCIe1 are 1-lane Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250416122538.2953658-2-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 525 +++++++++++++++++++++++++- 1 file changed, 521 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 5d6ed2172b1b..66bd2261eb25 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -157,6 +158,58 @@ #size-cells = <2>; ranges = <0 0 0 0 0x10 0>; + pcie0_phy: phy@84000 { + compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", + "qcom,ipq9574-qmp-gen3x1-pcie-phy"; + reg = <0x0 0x00084000 0x0 0x1000>; + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe"; + + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <0>; + clock-output-names = "gcc_pcie0_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + + pcie1_phy: phy@8c000 { + compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", + "qcom,ipq9574-qmp-gen3x1-pcie-phy"; + reg = <0x0 0x0008c000 0x0 0x1000>; + clocks = <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe"; + + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <0>; + clock-output-names = "gcc_pcie1_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + efuse@a4000 { compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; reg = <0 0x000a4000 0 0x741>; @@ -214,6 +267,58 @@ }; }; + pcie2_phy: phy@f4000 { + compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", + "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg = <0x0 0x000f4000 0x0 0x2000>; + clocks = <&gcc GCC_PCIE2_AUX_CLK>, + <&gcc GCC_PCIE2_AHB_CLK>, + <&gcc GCC_PCIE2_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe"; + + assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE2_PHY_BCR>, + <&gcc GCC_PCIE2PHY_PHY_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <0>; + clock-output-names = "gcc_pcie2_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + + pcie3_phy: phy@fc000 { + compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", + "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg = <0x0 0x000fc000 0x0 0x2000>; + clocks = <&gcc GCC_PCIE3_AUX_CLK>, + <&gcc GCC_PCIE3_AHB_CLK>, + <&gcc GCC_PCIE3_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe"; + + assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE3_PHY_BCR>, + <&gcc GCC_PCIE3PHY_PHY_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <0>; + clock-output-names = "gcc_pcie3_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + tsens: thermal-sensor@4a9000 { compatible = "qcom,ipq5424-tsens"; reg = <0 0x004a9000 0 0x1000>, @@ -281,10 +386,10 @@ reg = <0 0x01800000 0 0x40000>; clocks = <&xo_board>, <&sleep_clk>, - <0>, - <0>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, + <&pcie2_phy>, + <&pcie3_phy>, <0>; #clock-cells = <1>; #reset-cells = <1>; @@ -600,6 +705,418 @@ }; }; + pcie3: pcie@40000000 { + compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; + reg = <0x0 0x40000000 0x0 0xf1c>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x000f8000 0x0 0x3000>, + <0x0 0x40100000 0x0 0x1000>, + <0x0 0x000fe000 0x0 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <3>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x00100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x0fd00000>; + + msi-map = <0x0 &intc 0x0 0x1000>; + + interrupts = , + , + , + , + , + , + , + , + ; + + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 479 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 480 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 481 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 482 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, + <&gcc GCC_PCIE3_AXI_S_CLK>, + <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3_RCHNG_CLK>, + <&gcc GCC_PCIE3_AHB_CLK>, + <&gcc GCC_PCIE3_AUX_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + assigned-clocks = <&gcc GCC_PCIE3_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE3_PIPE_ARES>, + <&gcc GCC_PCIE3_CORE_STICKY_RESET>, + <&gcc GCC_PCIE3_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE3_AXI_S_ARES>, + <&gcc GCC_PCIE3_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE3_AXI_M_ARES>, + <&gcc GCC_PCIE3_AUX_ARES>, + <&gcc GCC_PCIE3_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie3_phy>; + phy-names = "pciephy"; + interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, + <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie2: pcie@50000000 { + compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; + reg = <0x0 0x50000000 0x0 0xf1c>, + <0x0 0x50000f20 0x0 0xa8>, + <0x0 0x50001000 0x0 0x1000>, + <0x0 0x000f0000 0x0 0x3000>, + <0x0 0x50100000 0x0 0x1000>, + <0x0 0x000f6000 0x0 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <2>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x0 0x50200000 0x0 0x00100000>, + <0x02000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000>; + + msi-map = <0x0 &intc 0x0 0x1000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 464 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 465 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 466 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 467 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, + <&gcc GCC_PCIE2_AXI_S_CLK>, + <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE2_RCHNG_CLK>, + <&gcc GCC_PCIE2_AHB_CLK>, + <&gcc GCC_PCIE2_AUX_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + assigned-clocks = <&gcc GCC_PCIE2_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE2_PIPE_ARES>, + <&gcc GCC_PCIE2_CORE_STICKY_RESET>, + <&gcc GCC_PCIE2_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE2_AXI_S_ARES>, + <&gcc GCC_PCIE2_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE2_AXI_M_ARES>, + <&gcc GCC_PCIE2_AUX_ARES>, + <&gcc GCC_PCIE2_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie2_phy>; + phy-names = "pciephy"; + interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, + <&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie1: pcie@60000000 { + compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; + reg = <0x0 0x60000000 0x0 0xf1c>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x1000>, + <0x0 0x00088000 0x0 0x3000>, + <0x0 0x60100000 0x0 0x1000>, + <0x0 0x0008e000 0x0 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <1>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x00100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x0fd00000>; + + msi-map = <0x0 &intc 0x0 0x1000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 450 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 451 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 452 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE1_RCHNG_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + assigned-clocks = <&gcc GCC_PCIE1_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE1_PIPE_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_ARES>, + <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_M_ARES>, + <&gcc GCC_PCIE1_AUX_ARES>, + <&gcc GCC_PCIE1_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, + <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie0: pcie@70000000 { + compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; + reg = <0x0 0x70000000 0x0 0xf1c>, + <0x0 0x70000f20 0x0 0xa8>, + <0x0 0x70001000 0x0 0x1000>, + <0x0 0x00080000 0x0 0x3000>, + <0x0 0x70100000 0x0 0x1000>, + <0x0 0x00086000 0x0 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x00100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000>; + + msi-map = <0x0 &intc 0x0 0x1000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 436 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 437 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + assigned-clocks = <&gcc GCC_PCIE0_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_ARES>, + <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_M_ARES>, + <&gcc GCC_PCIE0_AUX_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, + <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; }; thermal_zones: thermal-zones { -- 2.51.0