From a747c4dd2a60c4d0179b372032a4b98548135096 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:31 -0500 Subject: [PATCH 01/16] arm64: dts: imx8mn-beacon: Set SAI5 MCLK direction to output for HDMI audio The HDMI bridge chip fails to generate an audio source due to the SAI5 master clock (MCLK) direction not being set to output. This prevents proper clocking of the HDMI audio interface. Add the `fsl,sai-mclk-direction-output` property to the SAI5 node to ensure the MCLK is driven by the SoC, resolving the HDMI sound issue. Fixes: 1d6880ceef43 ("arm64: dts: imx8mn-beacon: Add HDMI video with sound") Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts index 1df5ceb11387..37fc5ed98d7f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts @@ -124,6 +124,7 @@ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; status = "okay"; }; -- 2.51.0 From 1c98ceb0d75e17aa59308ed0cf46e48b90006241 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:32 -0500 Subject: [PATCH 02/16] arm64: dts: imx8mm-beacon: Configure Ethernet PHY reset and GPIO IRQ The Ethernet PHY setup currently assumes that the bootloader will take the PHY out of reset, but this behavior is not guaranteed across all bootloaders. Add the reset GPIO to ensure the kernel can properly control the PHY reset line. Also configure the PHY IRQ GPIO to enable interrupt-driven link status reporting, instead of relying on polling. This ensures more reliable Ethernet initialization and improves PHY event handling. Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 9ba0cb89fa24..ed7a1be4a1a6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -78,6 +78,9 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -315,6 +318,7 @@ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 >; }; -- 2.51.0 From b08fc2f0fd99abc6cb2320fc58e2ff22a02f2b92 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:33 -0500 Subject: [PATCH 03/16] arm64: dts: imx8mn-beacon: Configure Ethernet PHY reset and GPIO IRQ The Ethernet PHY setup currently assumes that the bootloader will take the PHY out of reset, but this behavior is not guaranteed across all bootloaders. Add the reset GPIO to ensure the kernel can properly control the PHY reset line. Also configure the PHY IRQ GPIO to enable interrupt-driven link status reporting, instead of relying on polling. This ensures more reliable Ethernet initialization and improves PHY event handling. Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index bb11590473a4..b3692b367a42 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -88,6 +88,9 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -326,6 +329,7 @@ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 >; }; -- 2.51.0 From 2cb333ddd62f265be052842454e310c0a433b65a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:34 -0500 Subject: [PATCH 04/16] arm64: dts: imx8mm-beacon: Enable RTC interrupt and wakeup-source Enable the interrupts and wakeup-source to allow the external RTC to be used as an alarm. Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index ed7a1be4a1a6..c7a8f2a6fe90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -236,7 +236,12 @@ rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; quartz-load-femtofarads = <12500>; + wakeup-source; }; }; @@ -354,6 +359,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -- 2.51.0 From 12cc5a3898db7ea2ee756672f511a2cde370142a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:35 -0500 Subject: [PATCH 05/16] arm64: dts: imx8mn-beacon: Enable RTC interrupt and wakeup-source Enable the interrupts and wakeup-source to allow the external RTC to be used as an alarm. Signed-off-by: Adam Ford Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index b3692b367a42..987c14d3af9d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -245,7 +245,12 @@ rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; quartz-load-femtofarads = <12500>; + wakeup-source; }; }; @@ -365,6 +370,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 -- 2.51.0 From 8dd0e8a4966804e8aaf40c03e508191256e1437b Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 15 Apr 2025 20:01:36 -0500 Subject: [PATCH 06/16] arm64: dts: imx8mp-beacon: Enable RTC interrupt and wakeup-source Enable the interrupts and wakeup-source to allow the external RTC to be used as an alarm. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi index 88561df70d03..6a62cb32e22e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi @@ -257,7 +257,12 @@ rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; quartz-load-femtofarads = <12500>; + wakeup-source; }; }; @@ -382,6 +387,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1d0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 -- 2.51.0 From 14e66e4b13221d1b50291441600f5739abe50e09 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Thu, 17 Apr 2025 10:15:19 +0200 Subject: [PATCH 07/16] Revert "arm64: dts: imx93-tqma9352-mba93xxca: enable Open Drain for MDIO" Using the MDIO pins with Open Drain causes spec violations of the signals. Revert the changes. This reverts commit 9015397c2f2d9d327c0cf88d74e39c4858cb4912. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index ebbac5f8d2b2..137b8ed242a2 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -627,8 +627,8 @@ fsl,pins = < /* PD | FSEL_2 | DSE X4 */ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e - /* SION | HYS | ODE | FSEL_2 | DSE X4 */ - MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000191e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e /* HYS | FSEL_0 | DSE no drive */ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000 @@ -659,8 +659,8 @@ fsl,pins = < /* PD | FSEL_2 | DSE X4 */ MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e - /* SION | HYS | ODE | FSEL_2 | DSE X4 */ - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000191e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e /* HYS | FSEL_0 | DSE no drive */ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000 -- 2.51.0 From e05fae71e68f84c0743eda72fdddeee1e468e9e5 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Thu, 17 Apr 2025 10:15:20 +0200 Subject: [PATCH 08/16] Revert "arm64: dts: imx93-tqma9352-mba93xxla: enable Open Drain for MDIO" Using the MDIO pins with Open Drain causes spec violations of the signals. Revert the changes. This reverts commit 315d7f301e234b99c1b9619f0b14cf288dc7c33f. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index 9e88c42c3d17..219f49a4f87f 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -597,8 +597,8 @@ fsl,pins = < /* PD | FSEL_2 | DSE X4 */ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e - /* SION | HYS | ODE | FSEL_2 | DSE X4 */ - MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000191e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e /* HYS | FSEL_0 | DSE no drive */ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000 @@ -629,8 +629,8 @@ fsl,pins = < /* PD | FSEL_2 | DSE X4 */ MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e - /* SION | HYS | ODE | FSEL_2 | DSE X4 */ - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000191e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e /* HYS | FSEL_0 | DSE no drive */ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000 -- 2.51.0 From e2cfc140ae25cff0aae5a417adef0c0da61951c4 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 16 Apr 2025 17:13:41 +0200 Subject: [PATCH 09/16] arm64: dts: imx8-apalis: Add PCIe and SATA support The needed drivers to support PCIe and SATA for i.MX 8QM have been added. Configure them for the Apalis iMX8 SoM. The pciea and pcieb blocks each get a single PCIe lane, pciea is available on the carrier boards while pcieb is connected to the on module Wi-Fi/BT module. The SATA lane is available on the carrier boards. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-apalis-eval.dtsi | 10 ++- .../dts/freescale/imx8-apalis-ixora-v1.1.dtsi | 10 ++- .../dts/freescale/imx8-apalis-ixora-v1.2.dtsi | 10 ++- .../boot/dts/freescale/imx8-apalis-v1.1.dtsi | 70 ++++++++++++------- .../boot/dts/freescale/imx8qm-apalis.dtsi | 10 ++- 5 files changed, 74 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi index dc127298715b..311d4950793c 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi @@ -104,7 +104,10 @@ status = "okay"; }; -/* TODO: Apalis PCIE1 */ +/* Apalis PCIE1 */ +&pciea { + status = "okay"; +}; /* TODO: Apalis BKL1_PWM */ @@ -121,7 +124,10 @@ status = "okay"; }; -/* TODO: Apalis SATA1 */ +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; /* Apalis SPDIF1 */ &spdif0 { diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi index d4a1ad528f65..3d8731504ce1 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -191,7 +191,10 @@ status = "okay"; }; -/* TODO: Apalis PCIE1 */ +/* Apalis PCIE1 */ +&pciea { + status = "okay"; +}; /* TODO: Apalis BKL1_PWM */ @@ -208,7 +211,10 @@ status = "okay"; }; -/* TODO: Apalis SATA1 */ +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; /* Apalis SPDIF1 */ &spdif0 { diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi index 5e132c83e1b2..106e802a68ba 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi @@ -240,7 +240,10 @@ status = "okay"; }; -/* TODO: Apalis PCIE1 */ +/* Apalis PCIE1 */ +&pciea { + status = "okay"; +}; /* TODO: Apalis BKL1_PWM */ @@ -257,7 +260,10 @@ status = "okay"; }; -/* TODO: Apalis SATA1 */ +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; /* Apalis SPDIF1 */ &spdif0 { diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index dbea1eefdeec..6f27a9cc2494 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -339,6 +339,25 @@ pinctrl-0 = <&pinctrl_flexcan3>; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-pcieb-sata"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + +&hsio_refa_clk { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_sata_refclk>; + enable-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>; +}; + +&hsio_refb_clk { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_wifi_refclk>; + clocks = <&hsio_refa_clk>; + enable-gpios = <&lsio_gpio2 11 GPIO_ACTIVE_HIGH>; +}; + /* TODO: Apalis HDMI1 */ &gpu_alert0 { @@ -514,7 +533,10 @@ "MXM3_112", "MXM3_118", "MXM3_114", - "MXM3_116"; + "MXM3_116", + "", + "", + "MXM3_26"; }; &lsio_gpio1 { @@ -586,15 +608,6 @@ "MXM3_183", "MXM3_185", "MXM3_187"; - - pcie-wifi-hog { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_wifi_refclk>; - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - line-name = "PCIE_WIFI_CLK"; - output-high; - }; }; &lsio_gpio3 { @@ -660,16 +673,6 @@ "MXM3_291", "MXM3_289", "MXM3_287"; - - /* Enable pcie root / sata ref clock unconditionally */ - pcie-sata-hog { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_sata_refclk>; - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - line-name = "PCIE_SATA_CLK"; - output-high; - }; }; &lsio_gpio5 { @@ -771,9 +774,30 @@ status = "okay"; }; -/* TODO: Apalis PCIE1 */ +/* Apalis PCIE1 */ +&pciea { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + reset-gpio = <&lsio_gpio0 30 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_switch>; +}; + +/* On-module Wi-Fi */ +&pcieb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>, <&pinctrl_wifi>; + phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy"; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; -/* TODO: On-module Wi-Fi */ +&phyx2_lpcg { + clocks = <&hsio_refa_clk>, <&hsio_refb_clk>, + <&hsio_refa_clk>, <&hsio_per_clk>; +}; /* TODO: Apalis BKL1_PWM */ @@ -806,8 +830,6 @@ <722534400>, <45158400>, <11289600>, <49152000>; }; -/* TODO: Apalis SATA1 */ - /* Apalis SPDIF1 */ &spdif0 { assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi index c18f57039f6e..f97feee52c81 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi @@ -22,6 +22,10 @@ phy-mode = "rgmii-rxid"; }; +&hsio_refa_clk { + enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_HIGH>; +}; + /* TODO: Apalis HDMI1 */ /* Apalis I2C2 (DDC) */ @@ -188,12 +192,6 @@ "MXM3_291", "MXM3_289", "MXM3_287"; - - /* Enable pcie root / sata ref clock unconditionally */ - pcie-sata-hog { - gpios = <27 GPIO_ACTIVE_HIGH>; - }; - }; &lsio_gpio5 { -- 2.51.0 From 06d9879c106f683bd43bc9509ce444b11b863a83 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:23 -0400 Subject: [PATCH 10/16] arm64: dts: imx8: create unified pcie0 and pcie0_ep label for all chips Add unified pcie and pcie_ep label for existed chipes to prepare applied one overay file to enable EP function. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8dxl-ss-hsio.dtsi | 23 +++++++++++-------- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++-- .../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 6 ++--- .../boot/dts/freescale/imx8qxp-ss-hsio.dtsi | 6 +++++ 4 files changed, 24 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi index afbe962d78ce..67c5c6029cd9 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -37,15 +37,18 @@ power-domains = <&pd IMX_SC_R_SERDES_1>; status = "disabled"; }; -}; -&pcieb { - #interrupt-cells = <1>; - interrupts = ; - interrupt-names = "msi"; - interrupt-map = <0 0 0 1 &gic 0 47 4>, - <0 0 0 2 &gic 0 48 4>, - <0 0 0 3 &gic 0 49 4>, - <0 0 0 4 &gic 0 50 4>; - interrupt-map-mask = <0 0 0 0x7>; + pcie0: pcie@5f010000 { + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + interrupt-map = <0 0 0 1 &gic 0 47 4>, + <0 0 0 2 &gic 0 48 4>, + <0 0 0 3 &gic 0 49 4>, + <0 0 0 4 &gic 0 50 4>; + interrupt-map-mask = <0 0 0 0x7>; + }; + + pcie0_ep: pcie-ep@5f010000 { + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 75a1d02d39da..50a07c56faff 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -2153,7 +2153,7 @@ }; }; - pcie: pcie@33800000 { + pcie0: pcie: pcie@33800000 { compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config"; @@ -2191,7 +2191,7 @@ status = "disabled"; }; - pcie_ep: pcie-ep@33800000 { + pcie0_ep: pcie_ep: pcie-ep@33800000 { compatible = "fsl,imx8mp-pcie-ep"; reg = <0x33800000 0x100000>, <0x18000000 0x8000000>, diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index e80f722dbe65..50c0f6b0f0bd 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <1>; - pciea: pcie@5f000000 { + pcie0: pciea: pcie@5f000000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f000000 0x10000>, <0x4ff00000 0x80000>; @@ -42,7 +42,7 @@ status = "disabled"; }; - pciea_ep: pcie-ep@5f000000 { + pcie0_ep: pciea_ep: pcie-ep@5f000000 { compatible = "fsl,imx8q-pcie-ep"; reg = <0x5f000000 0x00010000>, <0x40000000 0x10000000>; @@ -61,7 +61,7 @@ status = "disabled"; }; - pcieb: pcie@5f010000 { + pcie1: pcieb: pcie@5f010000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi index 47fc6e0cff4a..255b8c91c88c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi @@ -38,4 +38,10 @@ power-domains = <&pd IMX_SC_R_SERDES_1>; status = "disabled"; }; + + pcie0: pcie@5f010000 { + }; + + pcie0_ep: pcie-ep@5f010000 { + }; }; -- 2.51.0 From 6f3287eae412a1bd3919a1085d4b72f13690fc97 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:24 -0400 Subject: [PATCH 11/16] arm64: dts: imx8dxl-ss-hsio: correct irq number for imx8dxl i.MX8DXL use difference irq number for PCIe EP DMA. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi index 67c5c6029cd9..bbc6abb0fdf2 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -50,5 +50,7 @@ }; pcie0_ep: pcie-ep@5f010000 { + interrupts = ; + interrupt-names = "dma"; }; }; -- 2.51.0 From c1c4820b60d7a2ad19c428aa8668c87adb0e6e80 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:25 -0400 Subject: [PATCH 12/16] arm64: dts: imx8dxl-evk: Add pcie0-ep node and use unified pcie0 label Use unified pcie0 label and add pcie0-ep node. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 5f3b4014e152..b6d64d3906ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -642,7 +642,7 @@ status = "okay"; }; -&pcieb { +&pcie0 { phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; @@ -652,6 +652,16 @@ status = "okay"; }; +&pcie0_ep{ + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcieb>; + status = "disabled"; +}; + &sai0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai0>; -- 2.51.0 From 1c9b0c6044c22835e2998d270ecca8a636e30294 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:26 -0400 Subject: [PATCH 13/16] arm64: dts: imx8: use common imx-pcie0-ep.dtso to enable PCI ep function Use common imx-pcie0-ep.dtso for imx8mp-evk-pcie-ep and imx8qxp-mek-pcie-ep. No functional change. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 8 +++++-- ...8mp-evk-pcie-ep.dtso => imx-pcie0-ep.dtso} | 6 ++--- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 8 ++++++- .../dts/freescale/imx8qxp-mek-pcie-ep.dtso | 22 ------------------- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 11 +++++++++- 5 files changed, 25 insertions(+), 30 deletions(-) rename arch/arm64/boot/dts/freescale/{imx8mp-evk-pcie-ep.dtso => imx-pcie0-ep.dtso} (64%) delete mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 186101781440..4f50cd5aa0f7 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -104,6 +104,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb + +imx8dxl-evk-pcie-ep-dtbs += imx8dxl-evk.dtb imx-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb @@ -239,7 +243,7 @@ imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds- imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtbo imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-lvds-hdmi.dtbo imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo -imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx8mp-evk-pcie-ep.dtbo +imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-lvds-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb @@ -286,7 +290,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb -imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx8qxp-mek-pcie-ep.dtbo +imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso b/arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso similarity index 64% rename from arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso rename to arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso index 244e820699b5..ed73284d9bb6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso +++ b/arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso @@ -6,12 +6,10 @@ /dts-v1/; /plugin/; -&pcie { +&pcie0 { status = "disabled"; }; -&pcie_ep { - pinctrl-0 = <&pinctrl_pcie0>; - pinctrl-names = "default"; +&pcie0_ep { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 9ab3ee93a35b..1ba3018c621e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -711,7 +711,7 @@ status = "okay"; }; -&pcie { +&pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; @@ -719,6 +719,12 @@ status = "okay"; }; +&pcie0_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + status = "disabled"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso deleted file mode 100644 index 4f562eb5c5b1..000000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2025 NXP - */ - -#include - -/dts-v1/; -/plugin/; - -&pcieb { - status = "disabled"; -}; - -&pcieb_ep { - phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; - phy-names = "pcie-phy"; - pinctrl-0 = <&pinctrl_pcieb>; - pinctrl-names = "default"; - vpcie-supply = <®_pcieb>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 4ba8ddd47223..c93d123670bd 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -537,7 +537,7 @@ status = "okay"; }; -&pcieb { +&pcie0 { phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; @@ -547,6 +547,15 @@ status = "okay"; }; +&pcie0_ep { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + vpcie-supply = <®_pcieb>; + status = "disabled"; +}; + &scu_key { status = "okay"; }; -- 2.51.0 From 58bea81052d0bf6e8fc438dda361569b72d3e8f1 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:27 -0400 Subject: [PATCH 14/16] arm64: dts: imx95: add pcie1 ep overlay file and create pcie-ep dtb files Create imx95-15x15-evk pcie0-ep and imx95-19x19-evk pcie[0,1]-ep dtb files. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 6 ++++++ arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso | 15 +++++++++++++++ arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 7 +++++++ arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 14 ++++++++++++++ 4 files changed, 42 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 4f50cd5aa0f7..51a97fd1dd58 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -312,6 +312,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb +imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb +imx95-19x19-evk-pcie0-ep-dtbs += imx95-19x19-evk.dtb imx-pcie0-ep.dtbo +imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep.dtb + imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb diff --git a/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso b/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso new file mode 100644 index 000000000000..0e7ef7ef8560 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; +/plugin/; + +&pcie1 { + status = "disabled"; +}; + +&pcie1_ep { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index aa0b9a4c3688..6c47f4b47356 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -534,6 +534,13 @@ status = "okay"; }; +&pcie0_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + vpcie-supply = <®_m2_pwr>; + status = "disabled"; +}; + &sai1 { assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index a41d542488ed..6886ea766655 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -426,6 +426,13 @@ status = "okay"; }; +&pcie0_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + vpcie-supply = <®_pcie0>; + status = "disabled"; +}; + &pcie1 { pinctrl-0 = <&pinctrl_pcie1>; pinctrl-names = "default"; @@ -434,6 +441,13 @@ status = "okay"; }; +&pcie1_ep { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + vpcie-supply = <®_slot_pwr>; + status = "disabled"; +}; + &sai1 { #sound-dai-cells = <0>; pinctrl-names = "default"; -- 2.51.0 From a705eb167ca4abd62b24540bcde19c592730caee Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:28 -0400 Subject: [PATCH 15/16] arm64: dts: imx8mm-evk: add pcie0-ep node and apply pcie0-ep overlay file Add pcie0-ep node information and apply pcie0-ep overlay file. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 5 +++++ arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 51a97fd1dd58..995f03ed28c9 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -116,6 +116,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb + +imx8mm-evk-pcie-ep-dtbs += imx8mm-evk.dtb imx-pcie0-ep.dtbo +imx8mm-evkb-pcie-ep-dtbs += imx8mm-evkb.dtb imx-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 5f8336217bb8..622caaa78eaf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -544,6 +544,19 @@ status = "okay"; }; +&pcie0_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "disabled"; +}; + &sai2 { #sound-dai-cells = <0>; pinctrl-names = "default"; -- 2.51.0 From 627b791541204a365ec64d4609ba3a98ff3aaccb Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Apr 2025 20:41:29 -0400 Subject: [PATCH 16/16] arm64: dts: imx8mq: add pcie0-ep node Add pcie0-ep node for i.MX8QM. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 07925b387677..c9040d1131a8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1770,6 +1770,41 @@ status = "disabled"; }; + pcie0_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mq-pcie-ep"; + reg = <0x33800000 0x100000>, + <0x18000000 0x8000000>, + <0x33900000 0x100000>, + <0x33b00000 0x100000>; + reg-names = "dbi", "addr_space", "dbi2", "atu"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + linux,pci-domain = <0>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; + num-ib-windows = <4>; + num-ob-windows = <4>; + fsl,max-link-speed = <2>; + status = "disabled"; + }; + pcie1: pcie@33c00000 { compatible = "fsl,imx8mq-pcie"; reg = <0x33c00000 0x400000>, -- 2.51.0