From a7dac91e56ae58e1479002e5b94fab73039f2e29 Mon Sep 17 00:00:00 2001 From: Prashanth K Date: Tue, 25 Mar 2025 18:00:16 +0530 Subject: [PATCH 01/16] arm64: dts: qcom: sm8350: Add snps,dis_u3_susphy_quirk During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250325123019.597976-3-prashanth.k@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 279a68a7146e..04a30df4362b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2652,6 +2652,7 @@ interrupts = ; iommus = <&apps_smmu 0x0 0x0>; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; @@ -2730,6 +2731,7 @@ interrupts = ; iommus = <&apps_smmu 0x20 0x0>; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; -- 2.51.0 From 9588f10adb5b67bea7eeebed2490c20dfbe82e77 Mon Sep 17 00:00:00 2001 From: Prashanth K Date: Tue, 25 Mar 2025 18:00:17 +0530 Subject: [PATCH 02/16] arm64: dts: qcom: sm8450: Add snps,dis_u3_susphy_quirk During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250325123019.597976-4-prashanth.k@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index a94188ecf384..54c6d0fdb2af 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5466,6 +5466,7 @@ interrupts = ; iommus = <&apps_smmu 0x0 0x0>; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; -- 2.51.0 From ad2011e02dab5ccc9f38848a3d909855a4ae7c8f Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Tue, 25 Mar 2025 18:00:18 +0530 Subject: [PATCH 03/16] arm64: dts: qcom: qcs615: Add snps,dis_u3_susphy_quirk During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. Signed-off-by: Pratham Pratap Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250325123019.597976-5-prashanth.k@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index edfb796d8dd3..7c377f3402c1 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3600,6 +3600,7 @@ snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; @@ -3661,6 +3662,7 @@ phy-names = "usb2-phy"; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; -- 2.51.0 From 25eee6c64376fcdc375b97c7e1f105e132654563 Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Tue, 25 Mar 2025 18:00:19 +0530 Subject: [PATCH 04/16] arm64: dts: qcom: qdu1000: Add snps,dis_u3_susphy_quirk During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. Signed-off-by: Pratham Pratap Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250325123019.597976-6-prashanth.k@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 7c8d78fd7ebf..846e5e5899aa 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1022,6 +1022,7 @@ iommus = <&apps_smmu 0xc0 0x0>; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; -- 2.51.0 From d8b462c44a0399e220a44c81cf562b909448bada Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Tue, 6 May 2025 15:37:47 +0200 Subject: [PATCH 05/16] arm64: dts: ipq6018: drop standalone 'smem' node Since commit b5af64fceb04 ("soc: qcom: smem: Support reserved-memory description") the SMEM device can be instantiated directly from a reserved-memory node. The 'smem' node is defined in this way for each modern IPQ SoCs except for IPQ6018. In order to make it inline with the others, move the 'compatible' and the 'hwlock' properties into the respective reserved-memory node, and drop the standalone 'smem' node. Signed-off-by: Gabor Juhos Reviewed-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20250506-ipq6018-drop-smem-v1-1-af99d177be2f@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index a02aa641cb90..7f0faf26b707 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -210,8 +210,11 @@ }; smem_region: memory@4aa00000 { + compatible = "qcom,smem"; reg = <0x0 0x4aa00000 0x0 0x100000>; no-map; + + hwlocks = <&tcsr_mutex 3>; }; q6_region: memory@4ab00000 { @@ -220,12 +223,6 @@ }; }; - smem { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - hwlocks = <&tcsr_mutex 3>; - }; - soc: soc@0 { #address-cells = <2>; #size-cells = <2>; -- 2.51.0 From 02a8b9894b9cbf4ffcd8661813826494cf49d3a2 Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Sun, 4 May 2025 14:51:18 +0300 Subject: [PATCH 06/16] arm64: dts: qcom: sdm630: Add modem metadata mem Similarly to MSM8998, add and use modem metadata memory region. This does not seemingly affect device functionality. But it fixes DTBs check warning: remoteproc@4080000: memory-region: [[45], [46]] is too short Signed-off-by: Alexey Minnekhanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250504115120.1432282-2-alexeymin@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 2d3820536ddf..8b1a45a4e56e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -509,6 +509,12 @@ reg = <0x0 0xfed00000 0x0 0xa00000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; smem: smem { @@ -1056,7 +1062,7 @@ <&rpmpd SDM660_VDDMX>; power-domain-names = "cx", "mx"; - memory-region = <&mba_region>, <&mpss_region>; + memory-region = <&mba_region>, <&mpss_region>, <&mdata_mem>; status = "disabled"; -- 2.51.0 From dbf62a117a1b7f605a98dd1fd1fd6c85ec324ea0 Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Sun, 4 May 2025 14:51:19 +0300 Subject: [PATCH 07/16] arm64: dts: qcom: sdm660-lavender: Add missing USB phy supply Fixes the following dtbs check error: phy@c012000: 'vdda-pll-supply' is a required property Fixes: e5d3e752b050e ("arm64: dts: qcom: sdm660-xiaomi-lavender: Add USB") Signed-off-by: Alexey Minnekhanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250504115120.1432282-3-alexeymin@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 0b4d71c14a77..a9926ad6c6f9 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -107,6 +107,7 @@ status = "okay"; vdd-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; }; -- 2.51.0 From f5110806b41eaa0eb0ab1bf2787876a580c6246c Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Sun, 4 May 2025 14:51:20 +0300 Subject: [PATCH 08/16] arm64: dts: qcom: sda660-ifc6560: Fix dt-validate warning If you remove clocks property, you should remove clock-names, too. Fixes warning with dtbs check: 'clocks' is a dependency of 'clock-names' Fixes: 34279d6e3f32c ("arm64: dts: qcom: sdm660: Add initial Inforce IFC6560 board support") Signed-off-by: Alexey Minnekhanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250504115120.1432282-4-alexeymin@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 4a5107689069..74cb29cb7f1a 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -175,6 +175,7 @@ * BAM DMA interconnects support is in place. */ /delete-property/ clocks; + /delete-property/ clock-names; }; &blsp1_uart2 { @@ -187,6 +188,7 @@ * BAM DMA interconnects support is in place. */ /delete-property/ clocks; + /delete-property/ clock-names; }; &blsp2_uart1 { -- 2.51.0 From 2ed8ee662660577a701e92917dbc65ca3553507c Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Wed, 30 Apr 2025 10:29:12 +0530 Subject: [PATCH 09/16] arm64: dts: qcom: qcs8300: Add cpufreq scaling node Add cpufreq-hw node to support cpufreq scaling on QCS8300. Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250430-qcs8300-cpufreq-scaling-v2-1-ee41566b8c56@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 037cd366a09b..9bc6cf9a3495 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -52,6 +52,7 @@ power-domain-names = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <472>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_0: l2-cache { compatible = "cache"; @@ -71,6 +72,7 @@ power-domain-names = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <472>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_1: l2-cache { compatible = "cache"; @@ -90,6 +92,7 @@ power-domain-names = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <507>; + qcom,freq-domain = <&cpufreq_hw 2>; l2_2: l2-cache { compatible = "cache"; @@ -109,6 +112,7 @@ power-domain-names = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <507>; + qcom,freq-domain = <&cpufreq_hw 2>; l2_3: l2-cache { compatible = "cache"; @@ -128,6 +132,7 @@ power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_4: l2-cache { compatible = "cache"; @@ -147,6 +152,7 @@ power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_5: l2-cache { compatible = "cache"; @@ -166,6 +172,7 @@ power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_6: l2-cache { compatible = "cache"; @@ -185,6 +192,7 @@ power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_7: l2-cache { compatible = "cache"; @@ -5279,6 +5287,28 @@ }; }; + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>, + <0x0 0x18594000 0x0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2"; + + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; + remoteproc_gpdsp: remoteproc@20c00000 { compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; reg = <0x0 0x20c00000 0x0 0x10000>; -- 2.51.0 From 9f2ae52acd5e6c95ddc55d1cc67f44860940a21b Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Sat, 26 Apr 2025 14:57:58 +0200 Subject: [PATCH 10/16] dt-bindings: arm: qcom: Add Asus Zenbook A14 Document the X1E-78-100 and X1P-42-100/X1-26-100 variants. Acked-by: Krzysztof Kozlowski Signed-off-by: Aleksandrs Vinarskis Link: https://lore.kernel.org/r/20250426130203.37659-3-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 08c329b1e919..bb589021a97a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1133,6 +1133,7 @@ properties: - items: - enum: - asus,vivobook-s15 + - asus,zenbook-a14-ux3407ra - dell,xps13-9345 - hp,omnibook-x14 - lenovo,yoga-slim7x @@ -1144,6 +1145,7 @@ properties: - items: - enum: + - asus,zenbook-a14-ux3407qa - qcom,x1p42100-crd - const: qcom,x1p42100 -- 2.51.0 From 099f3401dc3b7f4b63f9fa8b2f44f244c5ab3e62 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 24 Apr 2025 18:31:14 +0200 Subject: [PATCH 11/16] arm64: dts: qcom: sc7280: add UFS operating points Replace the deprecated freq-table-hz property with an operating points table with all supported frequencies and power levels. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250424-topic-sc7280-upstream-ufs-opps-v1-1-e63494d65f45@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 52 +++++++++++++++++++++++----- 1 file changed, 43 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 8e86d75cc6b4..911e104a219d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2364,18 +2364,52 @@ "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; + + operating-points-v2 = <&ufs_opp_table>; + qcom,ice = <&ice>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ufs_mem_phy: phy@1d87000 { -- 2.51.0 From 5ce920e6a8db40e4b094c0d863cbd19fdcfbbb7a Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 23 Apr 2025 09:30:07 +0200 Subject: [PATCH 12/16] arm64: dts: qcom: x1-crd: Fix vreg_l2j_1p2 voltage In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000 uV instead of the 1200000 uV we have currently in the device tree. Use the same for consistency and correctness. Cc: stable@vger.kernel.org Fixes: bd50b1f5b6f3 ("arm64: dts: qcom: x1e80100: Add Compute Reference Device") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-1-24b6a2043025@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index f73f053a46a0..dbdf542c7ce5 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -846,8 +846,8 @@ vreg_l2j_1p2: ldo2 { regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; regulator-initial-mode = ; }; -- 2.51.0 From 3ed2a9e03abfeece9e30ebc746f935536f661414 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 23 Apr 2025 09:30:08 +0200 Subject: [PATCH 13/16] arm64: dts: qcom: x1e001de-devkit: Fix vreg_l2j_1p2 voltage In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000 uV instead of the 1200000 uV we have currently in the device tree. Use the same for consistency and correctness. Cc: stable@vger.kernel.org Fixes: 7b8a31e82b87 ("arm64: dts: qcom: Add X1E001DE Snapdragon Devkit for Windows") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-2-24b6a2043025@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index 74911861a3bf..4693e4c9986a 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -747,8 +747,8 @@ vreg_l2j_1p2: ldo2 { regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; regulator-initial-mode = ; }; -- 2.51.0 From 0fb9ecf8713a7a458f7378c86e0703467db2ad22 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 23 Apr 2025 09:30:09 +0200 Subject: [PATCH 14/16] arm64: dts: qcom: x1e80100-asus-vivobook-s15: Fix vreg_l2j_1p2 voltage In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000 uV instead of the 1200000 uV we have currently in the device tree. Use the same for consistency and correctness. Cc: stable@vger.kernel.org Fixes: d0e2f8f62dff ("arm64: dts: qcom: Add device tree for ASUS Vivobook S 15") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-3-24b6a2043025@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index fb9567817be6..c94ddba5fbf1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -351,8 +351,8 @@ vreg_l2j_1p2: ldo2 { regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; regulator-initial-mode = ; }; -- 2.51.0 From 4a09dad9d437a13e9cd4383ff7791a816a6e1652 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 23 Apr 2025 09:30:10 +0200 Subject: [PATCH 15/16] arm64: dts: qcom: x1e80100-hp-omnibook-x14: Fix vreg_l2j_1p2 voltage In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000 uV instead of the 1200000 uV we have currently in the device tree. Use the same for consistency and correctness. Cc: stable@vger.kernel.org Fixes: 6f18b8d4142c ("arm64: dts: qcom: x1e80100-hp-x14: dt for HP Omnibook X Laptop 14") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-4-24b6a2043025@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index 1a187dc3684a..199e25674352 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -873,8 +873,8 @@ vreg_l2j_1p2: ldo2 { regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; regulator-initial-mode = ; }; -- 2.51.0 From 4f27ede34ca3369cdcde80c5a4ca84cdb28edbbb Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 23 Apr 2025 09:30:11 +0200 Subject: [PATCH 16/16] arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Fix vreg_l2j_1p2 voltage In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000 uV instead of the 1200000 uV we have currently in the device tree. Use the same for consistency and correctness. Cc: stable@vger.kernel.org Fixes: 45247fe17db2 ("arm64: dts: qcom: x1e80100: add Lenovo Thinkpad Yoga slim 7x devicetree") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-5-24b6a2043025@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 445d97d67d32..9fb306456e33 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -513,8 +513,8 @@ vreg_l2j_1p2: ldo2 { regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; regulator-initial-mode = ; }; -- 2.51.0