From cfe035d8662cfbd6edff9bd89c4b516bbb34c350 Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Wed, 14 May 2025 10:19:58 +0200 Subject: [PATCH 01/16] arm64: dts: mt6359: Rename RTC node to match binding expectations Rename the node 'mt6359rtc' to 'rtc', as required by the binding. Fix the following dtb-check error: mediatek/mt8395-radxa-nio-12l.dtb: pmic: 'mt6359rtc' do not match any of the regexes: 'pinctrl-[0-9]+' Fixes: 3b7d143be4b7 ("arm64: dts: mt6359: add PMIC MT6359 related nodes") Signed-off-by: Julien Massot Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250514-mt8395-dtb-errors-v2-3-d67b9077c59a@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6359.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi index 0c479404b3fe..467d8a4c2aa7 100644 --- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -300,7 +300,7 @@ }; }; - mt6359rtc: mt6359rtc { + mt6359rtc: rtc { compatible = "mediatek,mt6358-rtc"; }; }; -- 2.51.0 From 4a81656c8eaaa20675a3f67f452d02203c1e82f7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 20 May 2025 12:40:24 +0200 Subject: [PATCH 02/16] arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes Address various dt-binding warnings for most of the MDP3 nodes by adding and removing interrupts and power domains where required. Also, remove the mediatek,mt8195-mdp3-rdma fallback compatible from the main MDP3 RDMA node as the two have never really been fully compatible. Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250520104024.3706723-1-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 76 ++++++++++-------------- 1 file changed, 31 insertions(+), 45 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index dec6ce3e94e9..202478407727 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2243,27 +2243,17 @@ }; dma-controller@14001000 { - compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma"; + compatible = "mediatek,mt8188-mdp3-rdma"; reg = <0 0x14001000 0 0x1000>; #dma-cells = <1>; - clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>, - <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>, - <&topckgen CLK_TOP_CFGREG_F26M_VPP0>, - <&vppsys0 CLK_VPP0_WARP0_ASYNC_TX>, - <&vppsys0 CLK_VPP0_WARP0_RELAY>, - <&vppsys0 CLK_VPP0_WARP0_ASYNC>, - <&vppsys0 CLK_VPP02VPP1_RELAY>, - <&vppsys1 CLK_VPP1_VPP0_DL_ASYNC>, - <&vppsys1 CLK_VPP1_VPP0_DL1_RELAY>, - <&vppsys0 CLK_VPP0_VPP12VPP0_ASYNC>; + clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; mboxes = <&gce0 13 CMDQ_THR_PRIO_1>, <&gce0 14 CMDQ_THR_PRIO_1>, <&gce0 16 CMDQ_THR_PRIO_1>, - <&gce0 21 CMDQ_THR_PRIO_1>; - iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>, - <&vpp_iommu M4U_PORT_L4_MDP_WROT>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>, - <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + <&gce0 21 CMDQ_THR_PRIO_1>, + <&gce0 22 CMDQ_THR_PRIO_1>; + iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; mediatek,gce-events = , ; @@ -2274,7 +2264,6 @@ compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; reg = <0 0x14002000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_MDP_FG>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; }; @@ -2282,13 +2271,13 @@ compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; reg = <0 0x14004000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; }; display@14005000 { compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; reg = <0 0x14005000 0 0x1000>; + interrupts = ; clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; @@ -2298,21 +2287,22 @@ compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; reg = <0 0x14006000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events = , + ; }; display@14007000 { compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; reg = <0 0x14007000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; }; display@14008000 { compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; reg = <0 0x14008000 0 0x1000>; + interrupts = ; clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; @@ -2321,9 +2311,11 @@ display@14009000 { compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl"; reg = <0 0x14009000 0 0x1000>; + interrupts = ; clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; + iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>; }; display@1400a000 { @@ -2338,13 +2330,13 @@ compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc"; reg = <0 0x1400b000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; }; display@1400c000 { compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; reg = <0 0x1400c000 0 0x1000>; + #dma-cells = <1>; clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; @@ -2394,14 +2386,11 @@ }; dma-controller@14f09000 { - compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma"; + compatible = "mediatek,mt8188-mdp3-rdma"; reg = <0 0x14f09000 0 0x1000>; #dma-cells = <1>; - clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>, - <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, - <&topckgen CLK_TOP_CFGREG_F26M_VPP1>; - iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>, - <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; + iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; mediatek,gce-events = , @@ -2409,14 +2398,11 @@ }; dma-controller@14f0a000 { - compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma"; + compatible = "mediatek,mt8188-mdp3-rdma"; reg = <0 0x14f0a000 0 0x1000>; #dma-cells = <1>; - clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>, - <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, - <&topckgen CLK_TOP_CFGREG_F26M_VPP1>; - iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>, - <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; + iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; mediatek,gce-events = , @@ -2427,7 +2413,6 @@ compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; reg = <0 0x14f0c000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; }; @@ -2435,7 +2420,6 @@ compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; reg = <0 0x14f0d000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; }; @@ -2443,7 +2427,6 @@ compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; reg = <0 0x14f0f000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; }; @@ -2451,13 +2434,13 @@ compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; reg = <0 0x14f10000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; }; display@14f12000 { compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; reg = <0 0x14f12000 0 0x1000>; + interrupts = ; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; @@ -2466,6 +2449,7 @@ display@14f13000 { compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; reg = <0 0x14f13000 0 0x1000>; + interrupts = ; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; @@ -2474,26 +2458,25 @@ display@14f15000 { compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; reg = <0 0x14f15000 0 0x1000>; - clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>, - <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; + mediatek,gce-events = , + ; }; display@14f16000 { compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; reg = <0 0x14f16000 0 0x1000>; - clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>, - <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; + mediatek,gce-events = , + ; }; display@14f18000 { compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; reg = <0 0x14f18000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; }; @@ -2501,7 +2484,6 @@ compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; reg = <0 0x14f19000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; - power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; }; @@ -2524,6 +2506,7 @@ display@14f1d000 { compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; reg = <0 0x14f1d000 0 0x1000>; + interrupts = ; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; @@ -2532,6 +2515,7 @@ display@14f1e000 { compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; reg = <0 0x14f1e000 0 0x1000>; + interrupts = ; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; @@ -2558,6 +2542,7 @@ display@14f24000 { compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; reg = <0 0x14f24000 0 0x1000>; + #dma-cells = <1>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; @@ -2569,6 +2554,7 @@ display@14f25000 { compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; reg = <0 0x14f25000 0 0x1000>; + #dma-cells = <1>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; -- 2.51.0 From 99af08feb7fad3df79bda1628e4ee8b6eb1f6a32 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 20 May 2025 13:10:02 +0200 Subject: [PATCH 03/16] Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0" As clearly seen on other non-MediaTek platforms, this is known to eventually produce regressions in the future, as drivers may break ABI and stop working with older firmware versions. Although the firmware-name property was used in multiple MediaTek devicetrees for the System Companion Processor (SCP) node, avoid doing the same on MT8390 to lessen eventual ABI breakages that may happen with a driver update to change the firmware retrieval logic for the SCP. This reverts commit 2f0066dae66f30386ecd6408410e27a4d6818c15. Link: https://lore.kernel.org/r/20250520111002.282841-1-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index aa8dd12a84ea..eaf45d42cd34 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -1177,7 +1177,6 @@ }; &scp_c0 { - firmware-name = "mediatek/mt8188/scp.img"; memory-region = <&scp_mem>; status = "okay"; }; -- 2.51.0 From ede1fa1384c230c9823f6bf1849cf50c5fc8a83e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 20 May 2025 13:14:27 +0200 Subject: [PATCH 04/16] arm64: dts: rockchip: Add missing SFC power-domains to rk3576 Add the power-domains for the RK3576 SFC nodes according to the TRM part 1. This fixes potential SErrors when accessing the SFC registers without other peripherals (e.g. eMMC) doing a prior power-domain enable. For example this is easy to trigger on the Rock 4D, which enables the SFC0 interface, but does not enable the eMMC interface at the moment. Cc: stable@vger.kernel.org Fixes: 36299757129c8 ("arm64: dts: rockchip: Add SFC nodes for rk3576") Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20250520-rk3576-fix-fspi-pmdomain-v1-1-f07c6e62dadd@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 79800959b797..260f9598ee6c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1605,6 +1605,7 @@ interrupts = ; clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; clock-names = "clk_sfc", "hclk_sfc"; + power-domains = <&power RK3576_PD_SDGMAC>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1655,6 +1656,7 @@ interrupts = ; clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; clock-names = "clk_sfc", "hclk_sfc"; + power-domains = <&power RK3576_PD_NVM>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- 2.51.0 From 6e0f32da68fac556327666f8f81dfae7405d1c25 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Mon, 19 May 2025 12:18:28 +0200 Subject: [PATCH 05/16] arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588 The assigned-clocks and assigned-clock-rates properties were moved from the scmi_clk node onto cpu nodes in commit 87810bda8a84 ("arm64: dts: rockchip: Fix SCMI assigned clocks on rk3588s") During review of v1 of that patch set, the following comment was made: why aren't you using OPP tables to define CPU frequencies. Assigned-clocks looks like a temporary hack because you haven't done proper OPP tables. Some time later, proper OPP tables for rk3588 were added in commit 276856db91b4 ("arm64: dts: rockchip: Add OPP data for CPU cores on RK3588") So this 'temporary hack' is no longer needed. Dropping it fixes the following dtb validation issues: cpu@0: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) cpu@400: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) cpu@600: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) Link: https://lore.kernel.org/linux-rockchip/CAL_JsqL_EogoKOQ1xwU75=rJSC4o7yV3Jej4vadtacX2Pt3-hw@mail.gmail.com/ Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250519101909.62754-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 548677de9a53..70f03e68ba55 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -96,8 +96,6 @@ enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -174,8 +172,6 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -214,8 +210,6 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; -- 2.51.0 From 4d2587e0e1ce7145a38802fa281f4f1f411ec56f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 19 May 2025 00:04:43 +0200 Subject: [PATCH 06/16] arm64: dts: rockchip: fix rk3576 pcie unit addresses The rk3576 pcie nodes currently use the apb register as their unit address which is the second reg area defined in the binding. As can be seen by the dtc warnings like ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1346.24-1398.5: Warning (simple_bus_reg): /soc/pcie@2a200000: simple-bus unit address format error, expected "22000000" ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1400.24-1452.5: Warning (simple_bus_reg): /soc/pcie@2a210000: simple-bus unit address format error, expected "22400000" using the first reg area as the unit address seems to be preferred. This is the dbi area per the binding, so adapt the unit address accordingly and move the nodes to their new position. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/ Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250518220449.2722673-2-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 216 +++++++++++------------ 1 file changed, 108 insertions(+), 108 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 260f9598ee6c..500a144f6d23 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -466,6 +466,114 @@ #size-cells = <2>; ranges; + pcie0: pcie@22000000 { + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0x22000000 0x0 0x00400000>, + <0x0 0x2a200000 0x0 0x00010000>, + <0x0 0x20000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, + <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, + <&cru CLK_PCIE0_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + interrupts = , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3576_PD_PHP>; + ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 + 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 + 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie1: pcie@22400000 { + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0x22400000 0x0 0x00400000>, + <0x0 0x2a210000 0x0 0x00010000>, + <0x0 0x21000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, + <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, + <&cru CLK_PCIE1_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + interrupts = , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy1_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3576_PD_SUBPHP>; + ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 + 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 + 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + usb_drd0_dwc3: usb@23000000 { compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; reg = <0x0 0x23000000 0x0 0x400000>; @@ -1343,114 +1451,6 @@ reg = <0x0 0x27f22100 0x0 0x20>; }; - pcie0: pcie@2a200000 { - compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; - reg = <0x0 0x22000000 0x0 0x00400000>, - <0x0 0x2a200000 0x0 0x00010000>, - <0x0 0x20000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - bus-range = <0x0 0xf>; - clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, - <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, - <&cru CLK_PCIE0_AUX>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux"; - device_type = "pci"; - interrupts = , - , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - linux,pci-domain = <0>; - max-link-speed = <2>; - num-ib-windows = <8>; - num-viewport = <8>; - num-ob-windows = <2>; - num-lanes = <1>; - phys = <&combphy0_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3576_PD_PHP>; - ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 - 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 - 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; - resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie0_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie1: pcie@2a210000 { - compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; - reg = <0x0 0x22400000 0x0 0x00400000>, - <0x0 0x2a210000 0x0 0x00010000>, - <0x0 0x21000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - bus-range = <0x20 0x2f>; - clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, - <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, - <&cru CLK_PCIE1_AUX>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux"; - device_type = "pci"; - interrupts = , - , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - linux,pci-domain = <0>; - max-link-speed = <2>; - num-ib-windows = <8>; - num-viewport = <8>; - num-ob-windows = <2>; - num-lanes = <1>; - phys = <&combphy1_psu PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3576_PD_SUBPHP>; - ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 - 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 - 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; - resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - gmac0: ethernet@2a220000 { compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; reg = <0x0 0x2a220000 0x0 0x10000>; -- 2.51.0 From 8ff721f60257d550daf524fc559c0f0d2176b198 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 19 May 2025 00:04:44 +0200 Subject: [PATCH 07/16] arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:2351.20-2417.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/ Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250518220449.2722673-3-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 136 +++++++++++------------ 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 500a144f6d23..c73991b5f821 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -429,6 +429,74 @@ }; }; + pinctrl: pinctrl { + compatible = "rockchip,rk3576-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@27320000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x27320000 0x0 0x200>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2ae10000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae10000 0x0 0x200>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2ae20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae20000 0x0 0x200>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2ae30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae30000 0x0 0x200>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio4: gpio@2ae40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae40000 0x0 0x200>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + }; + pmu_a53: pmu-a53 { compatible = "arm,cortex-a53-pmu"; interrupts = , @@ -2349,74 +2417,6 @@ compatible = "arm,scmi-shmem"; reg = <0x0 0x4010f000 0x0 0x100>; }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3576-pinctrl"; - rockchip,grf = <&ioc_grf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@27320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x27320000 0x0 0x200>; - clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - interrupts = ; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2ae10000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae10000 0x0 0x200>; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 32>; - interrupts = ; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2ae20000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae20000 0x0 0x200>; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 64 32>; - interrupts = ; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2ae30000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae30000 0x0 0x200>; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - gpio-ranges = <&pinctrl 0 96 32>; - interrupts = ; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio4: gpio@2ae40000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae40000 0x0 0x200>; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - gpio-ranges = <&pinctrl 0 128 32>; - interrupts = ; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - }; }; }; -- 2.51.0 From f8b11d8cfbfc8a0232c1e7cc6af10583c8bdb3f1 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 19 May 2025 00:04:45 +0200 Subject: [PATCH 08/16] arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi Two empty lines between nodes, is one too many. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250518220449.2722673-4-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index c73991b5f821..1086482f0479 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -2002,7 +2002,6 @@ status = "disabled"; }; - i2c6: i2c@2ac90000 { compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0x2ac90000 0x0 0x1000>; -- 2.51.0 From 7d086f78fe09fb94eb3b2e12436f2feed21d9c1e Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 19 May 2025 00:04:46 +0200 Subject: [PATCH 09/16] arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3528.dtsi:870.20-936.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250518220449.2722673-5-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 136 +++++++++++------------ 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index b2724c969a76..d1c72b52aa4e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -95,6 +95,74 @@ }; }; + pinctrl: pinctrl { + compatible = "rockchip,rk3528-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff610000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff610000 0x0 0x200>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ffaf0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffaf0000 0x0 0x200>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ffb00000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb00000 0x0 0x200>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ffb10000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb10000 0x0 0x200>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ffb20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb20000 0x0 0x200>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -866,74 +934,6 @@ #dma-cells = <1>; arm,pl330-periph-burst; }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3528-pinctrl"; - rockchip,grf = <&ioc_grf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@ff610000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff610000 0x0 0x200>; - clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ffaf0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xffaf0000 0x0 0x200>; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 32 32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ffb00000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xffb00000 0x0 0x200>; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 64 32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ffb10000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xffb10000 0x0 0x200>; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 96 32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@ffb20000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xffb20000 0x0 0x200>; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 128 32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; }; }; -- 2.51.0 From 25d3e1d2558caf823902e3b1b83901f5ac65af8d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 19 May 2025 00:04:47 +0200 Subject: [PATCH 10/16] arm64: dts: rockchip: fix rk3562 pcie unit addresses The rk3562 pcie node currently uses the apb register as its unit address which is the second reg area defined in the binding. As can be seen by the dtc warnings like ../arch/arm64/boot/dts/rockchip/rk3562.dtsi:624.26-675.5: Warning (simple_bus_reg): /soc/pcie@ff500000: simple-bus unit address format error, expected "fe000000" using the first reg area as the unit address seems to be preferred. This is the dbi area per the binding, so adapt the unit address accordingly and move the nodes to their new position. With the move also move the reg + reg-names below the compatible, as is the preferred position. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250518220449.2722673-6-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 106 +++++++++++------------ 1 file changed, 53 insertions(+), 53 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 6268f84efa13..292e82ec5d45 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -249,6 +249,59 @@ #size-cells = <2>; ranges; + pcie2x1: pcie@fe000000 { + compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0xfe000000 0x0 0x400000>, + <0x0 0xff500000 0x0 0x10000>, + <0x0 0xfc000000 0x0 0x100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0xff>; + clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, + <0 0 0 2 &pcie2x1_intc 1>, + <0 0 0 3 &pcie2x1_intc 2>, + <0 0 0 4 &pcie2x1_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power 15>; + ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 + 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 + 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + gic: interrupt-controller@fe901000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -621,59 +674,6 @@ status = "disabled"; }; - pcie2x1: pcie@ff500000 { - compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x0 0xff>; - clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, - <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, - <&cru CLK_PCIE20_AUX>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; - device_type = "pci"; - interrupts = , - , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, - <0 0 0 2 &pcie2x1_intc 1>, - <0 0 0 3 &pcie2x1_intc 2>, - <0 0 0 4 &pcie2x1_intc 3>; - linux,pci-domain = <0>; - max-link-speed = <2>; - num-ib-windows = <8>; - num-viewport = <8>; - num-ob-windows = <2>; - num-lanes = <1>; - phys = <&combphy PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power 15>; - ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 - 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 - 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; - reg = <0x0 0xfe000000 0x0 0x400000>, - <0x0 0xff500000 0x0 0x10000>, - <0x0 0xfc000000 0x0 0x100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE20_POWERUP>; - reset-names = "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - spi1: spi@ff640000 { compatible = "rockchip,rk3066-spi"; reg = <0x0 0xff640000 0x0 0x1000>; -- 2.51.0 From dfab90b9580c2fbc4e8bb4ceee97cdd75832a6e7 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 19 May 2025 00:04:48 +0200 Subject: [PATCH 11/16] arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3562.dtsi:1115.20-1181.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250518220449.2722673-7-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 136 +++++++++++------------ 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 292e82ec5d45..def504ffa326 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -218,6 +218,74 @@ }; }; + pinctrl: pinctrl { + compatible = "rockchip,rk3562-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff260000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff260000 0x0 0x100>; + clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff620000 0x0 0x100>; + clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff630000 0x0 0x100>; + clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ffac0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffac0000 0x0 0x100>; + clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ffad0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffad0000 0x0 0x100>; + clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1111,74 +1179,6 @@ #io-channel-cells = <1>; status = "disabled"; }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3562-pinctrl"; - rockchip,grf = <&ioc_grf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@ff260000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff260000 0x0 0x100>; - clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - interrupts = ; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ff620000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff620000 0x0 0x100>; - clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 32>; - interrupts = ; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ff630000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff630000 0x0 0x100>; - clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 64 32>; - interrupts = ; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ffac0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xffac0000 0x0 0x100>; - clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; - gpio-controller; - gpio-ranges = <&pinctrl 0 96 32>; - interrupts = ; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio4: gpio@ffad0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xffad0000 0x0 0x100>; - clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; - gpio-controller; - gpio-ranges = <&pinctrl 0 128 32>; - interrupts = ; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - }; }; }; -- 2.51.0 From 24822c4b476c7d7387eec21711d7908a86728d8a Mon Sep 17 00:00:00 2001 From: Matthew Gerlach Date: Thu, 24 Apr 2025 07:43:41 -0700 Subject: [PATCH 12/16] dt-bindings: clock: socfpga: convert to yaml Convert the clock device tree bindings to yaml for the Altera SoCFPGA Cyclone5, Arria5, and Arria10 chip families. Since the clock nodes are subnodes to Altera SOCFPGA Clock Manager, the yaml was added to socfpga-clk-manager.yaml. Signed-off-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- .../arm/altera/socfpga-clk-manager.yaml | 102 +++++++++++++++++- .../bindings/clock/altr_socfpga.txt | 30 ------ 2 files changed, 101 insertions(+), 31 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/altr_socfpga.txt diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml index 572381306681..a758f4bb2bb3 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml @@ -9,20 +9,120 @@ title: Altera SOCFPGA Clock Manager maintainers: - Dinh Nguyen -description: test +description: + This binding describes the Altera SOCFGPA Clock Manager and its associated + tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10 + chip families. properties: compatible: items: - const: altr,clk-mgr + reg: maxItems: 1 + clocks: + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^osc[0-9]$": + type: object + + "^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$": + type: object + $ref: '#/$defs/clock-props' + unevaluatedProperties: false + + properties: + compatible: + enum: + - altr,socfpga-pll-clock + - altr,socfpga-perip-clk + - altr,socfpga-gate-clk + - altr,socfpga-a10-pll-clock + - altr,socfpga-a10-perip-clk + - altr,socfpga-a10-gate-clk + - fixed-clock + + clocks: + description: one or more phandles to input clock + minItems: 1 + maxItems: 5 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^[a-z0-9,_]+(clk|pll)(@[a-f0-9]+)?$": + type: object + $ref: '#/$defs/clock-props' + unevaluatedProperties: false + + properties: + compatible: + enum: + - altr,socfpga-perip-clk + - altr,socfpga-gate-clk + - altr,socfpga-a10-perip-clk + - altr,socfpga-a10-gate-clk + + clocks: + description: one or more phandles to input clock + minItems: 1 + maxItems: 4 + + required: + - compatible + - clocks + - "#clock-cells" + + required: + - compatible + - "#clock-cells" + required: - compatible + - reg additionalProperties: false +$defs: + clock-props: + properties: + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clk-gate: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: gating register offset + - description: bit index + + div-reg: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: divider register offset + - description: bit shift + - description: bit width + + fixed-divider: + $ref: /schemas/types.yaml#/definitions/uint32 + examples: - | clkmgr@ffd04000 { diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt deleted file mode 100644 index f72e80e0dade..000000000000 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ /dev/null @@ -1,30 +0,0 @@ -Device Tree Clock bindings for Altera's SoCFPGA platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "altr,socfpga-pll-clock" - for a PLL clock - "altr,socfpga-perip-clock" - The peripheral clock divided from the - PLL clock. - "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and - can get gated. - -- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. -- clocks : shall be the input parent clock phandle for the clock. This is - either an oscillator or a pll output. -- #clock-cells : from common clock binding, shall be set to 0. - -Optional properties: -- fixed-divider : If clocks have a fixed divider value, use this property. -- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register - and the bit index. -- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains - the divider register, bit shift, and width. -- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls - the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second - value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct - hold/delay times that is needed for the SD/MMC CIU clock. The values of both - can be 0-315 degrees, in 45 degree increments. -- 2.51.0 From c07da6de0eb87a328d8905585a9ca1076c6ee216 Mon Sep 17 00:00:00 2001 From: Nikolaos Pasaloukos Date: Mon, 12 May 2025 13:33:17 +0000 Subject: [PATCH 13/16] arm64: dts: blaize-blzp1600: Enable GPIO support Blaize BLZP1600 uses the custom silicon provided from VeriSilicon to add GPIO support. This interface is used to control signals on many other peripherals, such as Ethernet, USB, SD and eMMC. Signed-off-by: Nikolaos Pasaloukos Link: https://lore.kernel.org/r/20250512133302.151621-1-nikolaos.pasaloukos@blaize.com Signed-off-by: Arnd Bergmann --- .../boot/dts/blaize/blaize-blzp1600-cb2.dts | 36 +++++++++++++++++++ .../boot/dts/blaize/blaize-blzp1600.dtsi | 12 +++++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts index 7e3cef2ed352..fb5415eb347a 100644 --- a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts @@ -81,3 +81,39 @@ "UART1_TO_RSP"; /* GPIO_15 */ }; }; + +&gpio0 { + status = "okay"; + gpio-line-names = "PERST_N", /* GPIO_0 */ + "LM96063_ALERT_N", /* GPIO_1 */ + "INA3221_PV", /* GPIO_2 */ + "INA3221_CRIT", /* GPIO_3 */ + "INA3221_WARN", /* GPIO_4 */ + "INA3221_TC", /* GPIO_5 */ + "QSPI0_RST_N", /* GPIO_6 */ + "LM96063_TCRIT_N", /* GPIO_7 */ + "DSI_TCH_INT", /* GPIO_8 */ + "DSI_RST", /* GPIO_9 */ + "DSI_BL", /* GPIO_10 */ + "DSI_INT", /* GPIO_11 */ + "ETH_RST", /* GPIO_12 */ + "CSI0_RST", /* GPIO_13 */ + "CSI0_PWDN", /* GPIO_14 */ + "CSI1_RST", /* GPIO_15 */ + "CSI1_PWDN", /* GPIO_16 */ + "CSI2_RST", /* GPIO_17 */ + "CSI2_PWDN", /* GPIO_18 */ + "CSI3_RST", /* GPIO_19 */ + "CSI3_PWDN", /* GPIO_20 */ + "ADAC_RST", /* GPIO_21 */ + "SD_SW_VDD", /* GPIO_22 */ + "SD_PON_VDD", /* GPIO_23 */ + "GPIO_EXP_INT", /* GPIO_24 */ + "BOARD_ID_0", /* GPIO_25 */ + "SDIO1_SW_VDD", /* GPIO_26 */ + "SDIO1_PON_VDD", /* GPIO_27 */ + "SDIO2_SW_VDD", /* GPIO_28 */ + "SDIO2_PON_VDD", /* GPIO_29 */ + "BOARD_ID_1", /* GPIO_30 */ + "BOARD_ID_2"; /* GPIO_31 */ +}; diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi index 7d399e6a532f..5a6c882b2f57 100644 --- a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi @@ -120,6 +120,18 @@ IRQ_TYPE_LEVEL_LOW)>; }; + gpio0: gpio@4c0000 { + compatible = "blaize,blzp1600-gpio"; + reg = <0x4c0000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + uart0: serial@4d0000 { compatible = "ns16550a"; reg = <0x4d0000 0x1000>; -- 2.51.0 From 87901f69400a25bf5e24c71b4de42b18dab3beda Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 13 May 2025 12:10:24 +0200 Subject: [PATCH 14/16] ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings Recently DT bindings expect 'wifi' as node name: s5pv210-fascinate4g.dtb: wlan@1: $nodename:0: 'wlan@1' does not match '^wifi(@.*)?$' Link: https://lore.kernel.org/r/20250424084655.105011-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250513101023.21552-7-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/samsung/s5pv210-aries.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi b/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi index f628d3660493..153514e80c9a 100644 --- a/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi @@ -855,7 +855,7 @@ assigned-clock-rates = <0>, <50000000>; assigned-clock-parents = <&clocks MOUT_MPLL>; - wlan@1 { + wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gph2>; -- 2.51.0 From 7e1a0dfb3f5996c74cf39337ecd958342bffe442 Mon Sep 17 00:00:00 2001 From: "William A. Kennington III" Date: Thu, 15 May 2025 16:15:54 +0930 Subject: [PATCH 15/16] arm64: dts: nuvoton: Add pinctrl This is critical to support multifunction pins shared between devices as well as generic GPIOs. Signed-off-by: William A. Kennington III Link: https://patch.msgid.link/20250416015902.2091251-1-william@wkennington.com Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20250515-nuvoton-arm64-dt-v1-1-25769b8c1509@codeconstruct.com.au Signed-off-by: Arnd Bergmann --- .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index ecd171b2feba..fead4dde590d 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -176,4 +176,69 @@ }; }; }; + + pinctrl: pinctrl@f0010000 { + compatible = "nuvoton,npcm845-pinctrl"; + ranges = <0x0 0x0 0xf0010000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + nuvoton,sysgcr = <&gcr>; + status = "okay"; + gpio0: gpio@f0010000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0xB0>; + interrupts = ; + gpio-ranges = <&pinctrl 0 0 32>; + }; + gpio1: gpio@f0011000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0xB0>; + interrupts = ; + gpio-ranges = <&pinctrl 0 32 32>; + }; + gpio2: gpio@f0012000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0xB0>; + interrupts = ; + gpio-ranges = <&pinctrl 0 64 32>; + }; + gpio3: gpio@f0013000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x3000 0xB0>; + interrupts = ; + gpio-ranges = <&pinctrl 0 96 32>; + }; + gpio4: gpio@f0014000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x4000 0xB0>; + interrupts = ; + gpio-ranges = <&pinctrl 0 128 32>; + }; + gpio5: gpio@f0015000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x5000 0xB0>; + interrupts = ; + gpio-ranges = <&pinctrl 0 160 32>; + }; + gpio6: gpio@f0016000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x6000 0xB0>; + interrupts = ; + gpio-ranges = <&pinctrl 0 192 32>; + }; + gpio7: gpio@f0017000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x7000 0xB0>; + interrupts = ; + gpio-ranges = <&pinctrl 0 224 32>; + }; + }; }; -- 2.51.0 From 4c2cebc2e87d72857a66c121adb5ba1f72e3111f Mon Sep 17 00:00:00 2001 From: Sven Peter Date: Thu, 29 May 2025 00:17:18 +0200 Subject: [PATCH 16/16] MAINTAINERS, mailmap: update Sven Peter's email address Update my mail address to my new @kernel.org one and also add a mailmap entry to make sure everything gets sent there for easier filtering. Signed-off-by: Sven Peter Link: https://lore.kernel.org/r/20250528221718.45204-1-sven@kernel.org Signed-off-by: Arnd Bergmann --- .mailmap | 1 + MAINTAINERS | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/.mailmap b/.mailmap index 9afde79e1936..5dd7fbdf0de4 100644 --- a/.mailmap +++ b/.mailmap @@ -717,6 +717,7 @@ Sven Eckelmann Sven Eckelmann Sven Eckelmann Sven Eckelmann +Sven Peter Takashi YOSHII Tamizh Chelvam Raja Taniya Das diff --git a/MAINTAINERS b/MAINTAINERS index 1f6fbdd836fc..32268ba33e6e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2251,7 +2251,7 @@ F: sound/soc/codecs/cs42l84.* F: sound/soc/codecs/ssm3515.c ARM/APPLE MACHINE SUPPORT -M: Sven Peter +M: Sven Peter M: Janne Grunau R: Alyssa Rosenzweig R: Neal Gompa -- 2.51.0