From de39730f9258e9984892c0af68a3e884ad19acea Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Thu, 10 Apr 2025 19:03:18 +0530 Subject: [PATCH 01/16] phy: amlogic: phy-meson-axg-mipi-pcie-analog: Simplify error handling with dev_err_probe() Use dev_err_probe() for phy resources to indicate the deferral reason when waiting for the resource to come up. Signed-off-by: Anand Moon Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250410133332.294556-4-linux.amoon@gmail.com Signed-off-by: Vinod Koul --- drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c index ae898f93f97b..c0ba2852dbb8 100644 --- a/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c +++ b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c @@ -200,7 +200,6 @@ static int phy_axg_mipi_pcie_analog_probe(struct platform_device *pdev) struct phy_axg_mipi_pcie_analog_priv *priv; struct device_node *np = dev->of_node, *parent_np; struct regmap *map; - int ret; priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -219,12 +218,9 @@ static int phy_axg_mipi_pcie_analog_probe(struct platform_device *pdev) priv->regmap = map; priv->phy = devm_phy_create(dev, np, &phy_axg_mipi_pcie_analog_ops); - if (IS_ERR(priv->phy)) { - ret = PTR_ERR(priv->phy); - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to create PHY\n"); - return ret; - } + if (IS_ERR(priv->phy)) + return dev_err_probe(dev, PTR_ERR(priv->phy), + "failed to create PHY\n"); phy_set_drvdata(priv->phy, priv); dev_set_drvdata(dev, priv); -- 2.51.0 From a77e2e899841937798bff0924c03d4d0e4963aa3 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Thu, 10 Apr 2025 19:03:19 +0530 Subject: [PATCH 02/16] phy: amlogic: phy-meson-axg-mipi-dphy: Simplify error handling with dev_err_probe() Use dev_err_probe() for phy resources to indicate the deferral reason when waiting for the resource to come up. Signed-off-by: Anand Moon Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250410133332.294556-5-linux.amoon@gmail.com Signed-off-by: Vinod Koul --- drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c b/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c index 08a86962d949..c4a56b9d3289 100644 --- a/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c +++ b/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c @@ -377,13 +377,9 @@ static int phy_meson_axg_mipi_dphy_probe(struct platform_device *pdev) return ret; phy = devm_phy_create(dev, NULL, &phy_meson_axg_mipi_dphy_ops); - if (IS_ERR(phy)) { - ret = PTR_ERR(phy); - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to create PHY\n"); - - return ret; - } + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), + "failed to create PHY\n"); phy_set_drvdata(phy, priv); -- 2.51.0 From fef364bd4c9cf712c91e0013f5f304f4e7f09198 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Thu, 10 Apr 2025 19:03:20 +0530 Subject: [PATCH 03/16] phy: amlogic: phy-meson-axg-pcie: Simplify error handling with dev_err_probe() Use dev_err_probe() for phy resources to indicate the deferral reason when waiting for the resource to come up. Signed-off-by: Anand Moon Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250410133332.294556-6-linux.amoon@gmail.com Signed-off-by: Vinod Koul --- drivers/phy/amlogic/phy-meson-axg-pcie.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/phy/amlogic/phy-meson-axg-pcie.c b/drivers/phy/amlogic/phy-meson-axg-pcie.c index 60be5cdc600b..54baf7b8930e 100644 --- a/drivers/phy/amlogic/phy-meson-axg-pcie.c +++ b/drivers/phy/amlogic/phy-meson-axg-pcie.c @@ -131,19 +131,15 @@ static int phy_axg_pcie_probe(struct platform_device *pdev) struct phy_axg_pcie_priv *priv; struct device_node *np = dev->of_node; void __iomem *base; - int ret; priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->phy = devm_phy_create(dev, np, &phy_axg_pcie_ops); - if (IS_ERR(priv->phy)) { - ret = PTR_ERR(priv->phy); - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to create PHY\n"); - return ret; - } + if (IS_ERR(priv->phy)) + return dev_err_probe(dev, PTR_ERR(priv->phy), + "failed to create PHY\n"); base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) -- 2.51.0 From bdeff6d8a211c832f5ce1a65aff17f4a5e6de00f Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Thu, 10 Apr 2025 19:03:21 +0530 Subject: [PATCH 04/16] phy: amlogic: phy-meson-axg-pcie: Fix PHY creation order in axg-pcie probe Reorder the PHY creation in the axg-pcie probe function to ensure all the resource is mapped before creating the PHY. This change addresses the issue where the PHY creation was attempted before mapping the necessary resources, potentially causing failures. Signed-off-by: Anand Moon Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250410133332.294556-7-linux.amoon@gmail.com Signed-off-by: Vinod Koul --- drivers/phy/amlogic/phy-meson-axg-pcie.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/phy/amlogic/phy-meson-axg-pcie.c b/drivers/phy/amlogic/phy-meson-axg-pcie.c index 54baf7b8930e..14dee73f9cb5 100644 --- a/drivers/phy/amlogic/phy-meson-axg-pcie.c +++ b/drivers/phy/amlogic/phy-meson-axg-pcie.c @@ -136,11 +136,6 @@ static int phy_axg_pcie_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - priv->phy = devm_phy_create(dev, np, &phy_axg_pcie_ops); - if (IS_ERR(priv->phy)) - return dev_err_probe(dev, PTR_ERR(priv->phy), - "failed to create PHY\n"); - base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); @@ -158,6 +153,11 @@ static int phy_axg_pcie_probe(struct platform_device *pdev) if (IS_ERR(priv->analog)) return PTR_ERR(priv->analog); + priv->phy = devm_phy_create(dev, np, &phy_axg_pcie_ops); + if (IS_ERR(priv->phy)) + return dev_err_probe(dev, PTR_ERR(priv->phy), + "failed to create PHY\n"); + phy_set_drvdata(priv->phy, priv); dev_set_drvdata(dev, priv); pphy = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -- 2.51.0 From ea57d7fe4f5af517b5ce91fdff96cc33be932690 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Apr 2025 19:31:19 +0800 Subject: [PATCH 05/16] phy: qcom: pcie: Determine has_nocsr_reset dynamically Decide the in-driver logic based on whether the nocsr reset is present and defer checking the appropriateness of that to dt-bindings to save on boilerplate. Reset controller APIs are fine consuming a nullptr, so no additional checks are necessary there. Signed-off-by: Konrad Dybcio Signed-off-by: Wenbin Yao Reviewed-by: Abel Vesa Reviewed-by: Manivannan Sadhasivam Reviewed-by: Philipp Zabel Tested-by: Aleksandrs Vinarskis Link: https://lore.kernel.org/r/20250411113120.651363-2-quic_wenbyao@quicinc.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index c232b8fe9846..3fd911506f08 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3021,8 +3021,6 @@ struct qmp_phy_cfg { bool skip_start_delay; - bool has_nocsr_reset; - /* QMP PHY pipe clock interface rate */ unsigned long pipe_clock_rate; @@ -4020,7 +4018,6 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, - .has_nocsr_reset = true, /* 20MHz PHY AUX Clock */ .aux_clock_rate = 20000000, @@ -4053,7 +4050,6 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, - .has_nocsr_reset = true, /* 20MHz PHY AUX Clock */ .aux_clock_rate = 20000000, @@ -4173,7 +4169,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, - .has_nocsr_reset = true, }; static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { @@ -4207,7 +4202,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, - .has_nocsr_reset = true, }; static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { @@ -4239,7 +4233,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, - .has_nocsr_reset = true, }; static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = { @@ -4557,12 +4550,10 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) if (ret) return dev_err_probe(dev, ret, "failed to get resets\n"); - if (cfg->has_nocsr_reset) { - qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); - if (IS_ERR(qmp->nocsr_reset)) - return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), - "failed to get no-csr reset\n"); - } + qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr"); + if (IS_ERR(qmp->nocsr_reset)) + return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), + "failed to get no-csr reset\n"); return 0; } -- 2.51.0 From 0cc22f5a861c3149171485349dafac3047212a5d Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Fri, 11 Apr 2025 19:31:20 +0800 Subject: [PATCH 06/16] phy: qcom: qmp-pcie: Add PHY register retention support Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the whole PHY (hardware and register), no_csr reset only resets PHY hardware but retains register values, which means PHY setting can be skipped during PHY init if PCIe link is enabled in bootloader and only no_csr is toggled after that. Hence, determine whether the PHY has been enabled in bootloader by verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is available, skip BCR reset and PHY register setting to establish the PCIe link with bootloader - programmed PHY settings. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao Reviewed-by: Manivannan Sadhasivam Tested-by: Aleksandrs Vinarskis Link: https://lore.kernel.org/r/20250411113120.651363-3-quic_wenbyao@quicinc.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 69 ++++++++++++++++++++---- 1 file changed, 59 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 3fd911506f08..ab90aafb313e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3033,6 +3033,7 @@ struct qmp_pcie { const struct qmp_phy_cfg *cfg; bool tcsr_4ln_config; + bool skip_init; void __iomem *serdes; void __iomem *pcs; @@ -4330,18 +4331,38 @@ static int qmp_pcie_init(struct phy *phy) { struct qmp_pcie *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; + void __iomem *pcs = qmp->pcs; + bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL])); int ret; + qmp->skip_init = qmp->nocsr_reset && phy_initialized; + /* + * We need to check the existence of init sequences in two cases: + * 1. The PHY doesn't support no_csr reset. + * 2. The PHY supports no_csr reset but isn't initialized by bootloader. + * As we can't skip init in these two cases. + */ + if (!qmp->skip_init && !cfg->tbls.serdes_num) { + dev_err(qmp->dev, "Init sequence not available\n"); + return -ENODATA; + } + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); return ret; } - ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); - if (ret) { - dev_err(qmp->dev, "reset assert failed\n"); - goto err_disable_regulators; + /* + * Toggle BCR reset for PHY that doesn't support no_csr reset or has not + * been initialized. + */ + if (!qmp->skip_init) { + ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed\n"); + goto err_disable_regulators; + } } ret = reset_control_assert(qmp->nocsr_reset); @@ -4352,10 +4373,12 @@ static int qmp_pcie_init(struct phy *phy) usleep_range(200, 300); - ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); - if (ret) { - dev_err(qmp->dev, "reset deassert failed\n"); - goto err_assert_reset; + if (!qmp->skip_init) { + ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed\n"); + goto err_assert_reset; + } } ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); @@ -4365,7 +4388,8 @@ static int qmp_pcie_init(struct phy *phy) return 0; err_assert_reset: - reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (!qmp->skip_init) + reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); @@ -4377,7 +4401,10 @@ static int qmp_pcie_exit(struct phy *phy) struct qmp_pcie *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; - reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (qmp->nocsr_reset) + reset_control_assert(qmp->nocsr_reset); + else + reset_control_bulk_assert(cfg->num_resets, qmp->resets); clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); @@ -4396,6 +4423,13 @@ static int qmp_pcie_power_on(struct phy *phy) unsigned int mask, val; int ret; + /* + * Write CSR register for PHY that doesn't support no_csr reset or has not + * been initialized. + */ + if (qmp->skip_init) + goto skip_tbls_init; + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); @@ -4407,6 +4441,7 @@ static int qmp_pcie_power_on(struct phy *phy) qmp_pcie_init_registers(qmp, &cfg->tbls); qmp_pcie_init_registers(qmp, mode_tbls); +skip_tbls_init: ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); if (ret) return ret; @@ -4417,6 +4452,9 @@ static int qmp_pcie_power_on(struct phy *phy) goto err_disable_pipe_clk; } + if (qmp->skip_init) + goto skip_serdes_start; + /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); @@ -4426,6 +4464,7 @@ static int qmp_pcie_power_on(struct phy *phy) if (!cfg->skip_start_delay) usleep_range(1000, 1200); +skip_serdes_start: status = pcs + cfg->regs[QPHY_PCS_STATUS]; mask = cfg->phy_status; ret = readl_poll_timeout(status, val, !(val & mask), 200, @@ -4450,6 +4489,15 @@ static int qmp_pcie_power_off(struct phy *phy) clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); + /* + * While powering off the PHY, only qmp->nocsr_reset needs to be checked. In + * this way, no matter whether the PHY settings were initially programmed by + * bootloader or PHY driver itself, we can reuse them when PHY is powered on + * next time. + */ + if (qmp->nocsr_reset) + goto skip_phy_deinit; + /* PHY reset */ qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); @@ -4461,6 +4509,7 @@ static int qmp_pcie_power_off(struct phy *phy) qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); +skip_phy_deinit: return 0; } -- 2.51.0 From aae29082b6620c664e97a1e2f2062abc6a58659d Mon Sep 17 00:00:00 2001 From: Nitheesh Sekar Date: Wed, 26 Mar 2025 12:10:55 +0400 Subject: [PATCH 07/16] dt-bindings: phy: qcom: uniphy-pcie: Add ipq5018 compatible The IPQ5018 SoC contains a Gen2 1 and 2-lane PCIe UNIPHY which is the same as the one found in IPQ5332. As such, add IPQ5018 compatible. Signed-off-by: Nitheesh Sekar Signed-off-by: Sricharan Ramabadhran Reviewed-by: Rob Herring (Arm) Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20250326-ipq5018-pcie-v7-1-e1828fef06c9@outlook.com Signed-off-by: Vinod Koul --- .../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 49 ++++++++++++++++--- 1 file changed, 41 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml index e39168d55d23..6e9df81441e9 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml @@ -11,26 +11,24 @@ maintainers: - Varadarajan Narayanan description: - PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC + PCIe and USB combo PHY found in Qualcomm IPQ5018 & IPQ5332 SoCs properties: compatible: enum: + - qcom,ipq5018-uniphy-pcie-phy - qcom,ipq5332-uniphy-pcie-phy reg: maxItems: 1 clocks: - items: - - description: pcie pipe clock - - description: pcie ahb clock + minItems: 1 + maxItems: 2 resets: - items: - - description: phy reset - - description: ahb reset - - description: cfg reset + minItems: 2 + maxItems: 3 "#phy-cells": const: 0 @@ -53,6 +51,41 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-uniphy-pcie-phy + then: + properties: + clocks: + items: + - description: pcie pipe clock + resets: + items: + - description: phy reset + - description: cfg reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-uniphy-pcie-phy + then: + properties: + clocks: + items: + - description: pcie pipe clock + - description: pcie ahb clock + resets: + items: + - description: phy reset + - description: ahb reset + - description: cfg reset + examples: - | #include -- 2.51.0 From dfc820d2f8a8ea90bbc02269b5362e3678e58cac Mon Sep 17 00:00:00 2001 From: Nitheesh Sekar Date: Wed, 26 Mar 2025 12:10:56 +0400 Subject: [PATCH 08/16] phy: qualcomm: qcom-uniphy-pcie 28LP add support for IPQ5018 The Qualcomm UNIPHY PCIe PHY 28LP is found on both IPQ5332 and IPQ5018. Adding the PHY init sequence, pipe clock rate, and compatible for IPQ5018. Signed-off-by: Nitheesh Sekar Signed-off-by: Sricharan Ramabadhran Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20250326-ipq5018-pcie-v7-2-e1828fef06c9@outlook.com Signed-off-by: Vinod Koul --- .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c index c8b2a3818880..324c0a5d658e 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c @@ -75,6 +75,40 @@ struct qcom_uniphy_pcie { #define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy) +static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = { + { + .offset = SSCG_CTRL_REG_4, + .val = 0x1cb9, + }, { + .offset = SSCG_CTRL_REG_5, + .val = 0x023a, + }, { + .offset = SSCG_CTRL_REG_3, + .val = 0xd360, + }, { + .offset = SSCG_CTRL_REG_1, + .val = 0x1, + }, { + .offset = SSCG_CTRL_REG_2, + .val = 0xeb, + }, { + .offset = CDR_CTRL_REG_4, + .val = 0x3f9, + }, { + .offset = CDR_CTRL_REG_5, + .val = 0x1c9, + }, { + .offset = CDR_CTRL_REG_2, + .val = 0x419, + }, { + .offset = CDR_CTRL_REG_1, + .val = 0x200, + }, { + .offset = PCS_INTERNAL_CONTROL_2, + .val = 0xf101, + }, +}; + static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { { .offset = PHY_CFG_PLLCFG, @@ -88,6 +122,14 @@ static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { }, }; +static const struct qcom_uniphy_pcie_data ipq5018_data = { + .lane_offset = 0x800, + .phy_type = PHY_TYPE_PCIE_GEN2, + .init_seq = ipq5018_regs, + .init_seq_num = ARRAY_SIZE(ipq5018_regs), + .pipe_clk_rate = 125 * MEGA, +}; + static const struct qcom_uniphy_pcie_data ipq5332_data = { .lane_offset = 0x800, .phy_type = PHY_TYPE_PCIE_GEN3, @@ -212,6 +254,9 @@ static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id) static const struct of_device_id qcom_uniphy_pcie_id_table[] = { { + .compatible = "qcom,ipq5018-uniphy-pcie-phy", + .data = &ipq5018_data, + }, { .compatible = "qcom,ipq5332-uniphy-pcie-phy", .data = &ipq5332_data, }, { -- 2.51.0 From 10ed34d6eaaf86e301a8f2dd190d26dfbc9799bd Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Tue, 18 Mar 2025 14:35:35 +0200 Subject: [PATCH 09/16] phy: Add HDMI configuration options Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union. The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users. Signed-off-by: Sandor Yu Reviewed-by: Dmitry Baryshkov Reviewed-by: Maxime Ripard Acked-by: Vinod Koul Link: https://lore.kernel.org/r/d1cff6c03ec3732d2244022029245ab2d954d997.1734340233.git.Sandor.yu@nxp.com Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-1-8cb1678e7663@collabora.com Signed-off-by: Vinod Koul --- include/linux/phy/phy-hdmi.h | 19 +++++++++++++++++++ include/linux/phy/phy.h | 7 ++++++- 2 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 include/linux/phy/phy-hdmi.h diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h new file mode 100644 index 000000000000..6a696922bc7f --- /dev/null +++ b/include/linux/phy/phy-hdmi.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2022,2024 NXP + */ + +#ifndef __PHY_HDMI_H_ +#define __PHY_HDMI_H_ + +/** + * struct phy_configure_opts_hdmi - HDMI configuration set + * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. + * + * This structure is used to represent the configuration state of a HDMI phy. + */ +struct phy_configure_opts_hdmi { + unsigned long long tmds_char_rate; +}; + +#endif /* __PHY_HDMI_H_ */ diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index e63e6e70e860..437769e061b7 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -17,6 +17,7 @@ #include #include +#include #include #include @@ -42,7 +43,8 @@ enum phy_mode { PHY_MODE_MIPI_DPHY, PHY_MODE_SATA, PHY_MODE_LVDS, - PHY_MODE_DP + PHY_MODE_DP, + PHY_MODE_HDMI, }; enum phy_media { @@ -60,11 +62,14 @@ enum phy_media { * the DisplayPort protocol. * @lvds: Configuration set applicable for phys supporting * the LVDS phy mode. + * @hdmi: Configuration set applicable for phys supporting + * the HDMI phy mode. */ union phy_configure_opts { struct phy_configure_opts_mipi_dphy mipi_dphy; struct phy_configure_opts_dp dp; struct phy_configure_opts_lvds lvds; + struct phy_configure_opts_hdmi hdmi; }; /** -- 2.51.0 From 3bb9286f4ece6acbc1fbaa9f192a82645d30efbf Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 18 Mar 2025 14:35:36 +0200 Subject: [PATCH 10/16] phy: hdmi: Add color depth configuration Extend the HDMI configuration options to allow managing bits per color channel. This is required by some PHY drivers such as rockchip-samsung-hdptx. Reviewed-by: Dmitry Baryshkov Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-2-8cb1678e7663@collabora.com Signed-off-by: Vinod Koul --- include/linux/phy/phy-hdmi.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h index 6a696922bc7f..f0ec963c6e84 100644 --- a/include/linux/phy/phy-hdmi.h +++ b/include/linux/phy/phy-hdmi.h @@ -9,11 +9,13 @@ /** * struct phy_configure_opts_hdmi - HDMI configuration set * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. + * @bpc: Bits per color channel. * * This structure is used to represent the configuration state of a HDMI phy. */ struct phy_configure_opts_hdmi { unsigned long long tmds_char_rate; + unsigned int bpc; }; #endif /* __PHY_HDMI_H_ */ -- 2.51.0 From 0422253ac1919fea8292381c85f11a9decff1bb1 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 18 Mar 2025 14:35:37 +0200 Subject: [PATCH 11/16] phy: rockchip: samsung-hdptx: Fix clock ratio setup The switch from 1/10 to 1/40 clock ratio must happen when exceeding the 340 MHz rate limit of HDMI 1.4, i.e. when entering the HDMI 2.0 domain, and not before. Therefore, use the correct comparison operator '>' instead of '>=' when checking the max rate. While at it, introduce a define for this rate limit constant. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Reviewed-by: Dmitry Baryshkov Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-3-8cb1678e7663@collabora.com Signed-off-by: Vinod Koul --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index fe7c05748356..34a7ef209364 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -320,6 +320,7 @@ #define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3) #define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2) +#define HDMI14_MAX_RATE 340000000 #define HDMI20_MAX_RATE 600000000 enum dp_link_rate { @@ -1072,7 +1073,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); - if (rate >= 3400000) { + if (rate > HDMI14_MAX_RATE / 100) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); } else { -- 2.51.0 From 1f4d382769e3b38dfc498c806811dae856e40f31 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 18 Mar 2025 14:35:38 +0200 Subject: [PATCH 12/16] phy: rockchip: samsung-hdptx: Do no set rk_hdptx_phy->rate in case of errors Ensure rk_hdptx_ropll_tmds_cmn_config() updates hdptx->rate only after all the other operations have been successful. Fixes: c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support") Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-4-8cb1678e7663@collabora.com Signed-off-by: Vinod Koul --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 34a7ef209364..d0989dc5a017 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1006,9 +1006,7 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, { const struct ropll_config *cfg = NULL; struct ropll_config rc = {0}; - int i; - - hdptx->rate = rate * 100; + int ret, i; for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) if (rate == ropll_tmds_cfg[i].bit_rate) { @@ -1063,7 +1061,11 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); - return rk_hdptx_post_enable_pll(hdptx); + ret = rk_hdptx_post_enable_pll(hdptx); + if (!ret) + hdptx->rate = rate * 100; + + return ret; } static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, -- 2.51.0 From 6218c3fd6702a5bc4ab323fed25714cde127684c Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 18 Mar 2025 14:35:39 +0200 Subject: [PATCH 13/16] phy: rockchip: samsung-hdptx: Drop unused struct lcpll_config This is just a leftover from downstream support for HDMI 2.1. Remove the unused struct for now. Reviewed-by: Dmitry Baryshkov Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-5-8cb1678e7663@collabora.com Signed-off-by: Vinod Koul --- .../phy/rockchip/phy-rockchip-samsung-hdptx.c | 31 ------------------- 1 file changed, 31 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index d0989dc5a017..70621687b5eb 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -329,37 +329,6 @@ enum dp_link_rate { DP_BW_HBR2, }; -struct lcpll_config { - u32 bit_rate; - u8 lcvco_mode_en; - u8 pi_en; - u8 clk_en_100m; - u8 pms_mdiv; - u8 pms_mdiv_afc; - u8 pms_pdiv; - u8 pms_refdiv; - u8 pms_sdiv; - u8 pi_cdiv_rstn; - u8 pi_cdiv_sel; - u8 sdm_en; - u8 sdm_rstn; - u8 sdc_frac_en; - u8 sdc_rstn; - u8 sdm_deno; - u8 sdm_num_sign; - u8 sdm_num; - u8 sdc_n; - u8 sdc_n2; - u8 sdc_num; - u8 sdc_deno; - u8 sdc_ndiv_rstn; - u8 ssc_en; - u8 ssc_fm_dev; - u8 ssc_fm_freq; - u8 ssc_clk_div_sel; - u8 cd_tx_ser_rate_sel; -}; - struct ropll_config { u32 bit_rate; u8 pms_mdiv; -- 2.51.0 From bcd61d182618c6a77d0841fcdc3333e125725360 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 18 Mar 2025 14:35:40 +0200 Subject: [PATCH 14/16] phy: rockchip: samsung-hdptx: Drop unused phy_cfg driver data There is no usage of phy_cfg in the upstream driver data, nor in the downstream one, hence remove it. Reviewed-by: Dmitry Baryshkov Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-6-8cb1678e7663@collabora.com Signed-off-by: Vinod Koul --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 70621687b5eb..c9f79c4e698c 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -397,7 +397,6 @@ struct rk_hdptx_phy { int phy_id; struct phy *phy; - struct phy_config *phy_cfg; struct clk_bulk_data *clks; int nr_clks; struct reset_control_bulk_data rsts[RST_MAX]; -- 2.51.0 From bacf2fe750dab6bc7ed50556aaadd3ab107fc643 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 18 Mar 2025 14:35:41 +0200 Subject: [PATCH 15/16] phy: rockchip: samsung-hdptx: Drop superfluous cfgs driver data The ->cfgs member has been introduced via commit f08d1c085638 ("phy: phy-rockchip-samsung-hdptx: Don't use dt aliases to determine phy-id"), but it is only used during probe() in order to setup ->phy_id. Use a probe() local variable to store device match data and remove the now unnecessary member from struct rk_hdptx_phy. Reviewed-by: Dmitry Baryshkov Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-7-8cb1678e7663@collabora.com Signed-off-by: Vinod Koul --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index c9f79c4e698c..2c0ae2442842 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -392,10 +392,7 @@ struct rk_hdptx_phy { struct regmap *regmap; struct regmap *grf; - /* PHY const config */ - const struct rk_hdptx_phy_cfg *cfgs; int phy_id; - struct phy *phy; struct clk_bulk_data *clks; int nr_clks; @@ -1894,6 +1891,7 @@ static int rk_hdptx_phy_runtime_resume(struct device *dev) static int rk_hdptx_phy_probe(struct platform_device *pdev) { + const struct rk_hdptx_phy_cfg *cfgs; struct phy_provider *phy_provider; struct device *dev = &pdev->dev; struct rk_hdptx_phy *hdptx; @@ -1912,14 +1910,14 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(regs), "Failed to ioremap resource\n"); - hdptx->cfgs = device_get_match_data(dev); - if (!hdptx->cfgs) + cfgs = device_get_match_data(dev); + if (!cfgs) return dev_err_probe(dev, -EINVAL, "missing match data\n"); /* find the phy-id from the io address */ hdptx->phy_id = -ENODEV; - for (id = 0; id < hdptx->cfgs->num_phys; id++) { - if (res->start == hdptx->cfgs->phy_ids[id]) { + for (id = 0; id < cfgs->num_phys; id++) { + if (res->start == cfgs->phy_ids[id]) { hdptx->phy_id = id; break; } -- 2.51.0 From 0edf9d2bb9b4ba7566dfdc7605883e04575129d9 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 18 Mar 2025 14:35:42 +0200 Subject: [PATCH 16/16] phy: rockchip: samsung-hdptx: Avoid Hz<->hHz unit conversion overhead The ropll_tmds_cfg table used to identify the configuration params for the supported rates expects the search key, i.e. bit_rate member of struct ropll_config, to be provided in hHz rather than Hz (1 hHz = 100 Hz). This requires multiple conversions between these units being performed at runtime. Improve implementation clarity and efficiency by consistently using the Hz unit throughout driver's internal data structures and functions. Also rename the rather misleading struct member. Signed-off-by: Cristian Ciocaltea Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-8-8cb1678e7663@collabora.com Signed-off-by: Vinod Koul --- .../phy/rockchip/phy-rockchip-samsung-hdptx.c | 79 +++++++++---------- 1 file changed, 39 insertions(+), 40 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 2c0ae2442842..e4f6b1d6d999 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -330,7 +330,7 @@ enum dp_link_rate { }; struct ropll_config { - u32 bit_rate; + unsigned long long rate; u8 pms_mdiv; u8 pms_mdiv_afc; u8 pms_pdiv; @@ -410,45 +410,45 @@ struct rk_hdptx_phy { }; static const struct ropll_config ropll_tmds_cfg[] = { - { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 297000000ULL, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, + { 162000000ULL, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 185625000ULL, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, + { 154000000ULL, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, + { 148500000ULL, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, + { 146250000ULL, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, + { 119000000ULL, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, + { 106500000ULL, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 108000000ULL, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, + { 85500000ULL, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, + { 83500000ULL, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 92812500ULL, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 74250000ULL, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, + { 65000000ULL, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, + { 33750000ULL, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 40000000ULL, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 27000000ULL, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, + { 25175000ULL, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, }; @@ -894,10 +894,10 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx) regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); } -static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, +static bool rk_hdptx_phy_clk_pll_calc(unsigned long long rate, struct ropll_config *cfg) { - const unsigned int fout = data_rate / 2, fref = 24000; + const unsigned int fout = div_u64(rate, 200), fref = 24000; unsigned long k = 0, lc, k_sub, lc_sub; unsigned int fvco, sdc; u32 mdiv, sdiv, n = 8; @@ -967,14 +967,14 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, } static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, - unsigned int rate) + unsigned long long rate) { const struct ropll_config *cfg = NULL; struct ropll_config rc = {0}; int ret, i; for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (rate == ropll_tmds_cfg[i].bit_rate) { + if (rate == ropll_tmds_cfg[i].rate) { cfg = &ropll_tmds_cfg[i]; break; } @@ -988,8 +988,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, } } - dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u, sdm_en=%u, k_sign=%u, k=%u, lc=%u\n", - cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en, + dev_dbg(hdptx->dev, "%s rate=%llu mdiv=%u sdiv=%u sdm_en=%u k_sign=%u k=%u lc=%u\n", + __func__, rate, cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); rk_hdptx_pre_power_up(hdptx); @@ -1028,19 +1028,19 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, ret = rk_hdptx_post_enable_pll(hdptx); if (!ret) - hdptx->rate = rate * 100; + hdptx->rate = rate; return ret; } static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, - unsigned int rate) + unsigned long long rate) { rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); - if (rate > HDMI14_MAX_RATE / 100) { + if (rate > HDMI14_MAX_RATE) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); } else { @@ -1093,7 +1093,7 @@ static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx) } static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx, - unsigned int rate) + unsigned long long rate) { enum phy_mode mode = phy_get_mode(hdptx->phy); u32 status; @@ -1411,8 +1411,8 @@ static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy *hdptx) static int rk_hdptx_phy_power_on(struct phy *phy) { struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); - int bus_width = phy_get_bus_width(hdptx->phy); enum phy_mode mode = phy_get_mode(phy); + unsigned long long rate; int ret, lane; /* @@ -1420,10 +1420,10 @@ static int rk_hdptx_phy_power_on(struct phy *phy) * from the HDMI bridge driver until phy_configure_opts_hdmi * becomes available in the PHY API. */ - unsigned int rate = bus_width & 0xfffffff; + rate = phy_get_bus_width(hdptx->phy) & 0xfffffff; + rate *= 100; - dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n", - __func__, bus_width, rate); + dev_dbg(hdptx->dev, "%s rate=%llu\n", __func__, rate); ret = rk_hdptx_phy_consumer_get(hdptx, rate); if (ret) @@ -1785,7 +1785,7 @@ static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw) { struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); - return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100); + return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate); } static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw) @@ -1806,18 +1806,17 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - u32 bit_rate = rate / 100; int i; if (rate > HDMI20_MAX_RATE) return rate; for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (bit_rate == ropll_tmds_cfg[i].bit_rate) + if (rate == ropll_tmds_cfg[i].rate) break; if (i == ARRAY_SIZE(ropll_tmds_cfg) && - !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) + !rk_hdptx_phy_clk_pll_calc(rate, NULL)) return -EINVAL; return rate; @@ -1828,7 +1827,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, { struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); - return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); + return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); } static const struct clk_ops hdptx_phy_clk_ops = { -- 2.51.0