From f9ced7dbbb551885c63632f1594997bdaf2177ee Mon Sep 17 00:00:00 2001 From: V sujith kumar Reddy Date: Wed, 23 Nov 2022 17:49:09 +0530 Subject: [PATCH] ASoC: SOF: amd: Fix for selecting clock source as external clock. By default clock source is selected as internal clock of 96Mhz which is not configurable. Now we select the clock source to external clock (ACLK) which can be configurable to different clock ranges depending on usecase. Signed-off-by: V sujith kumar Reddy Link: https://lore.kernel.org/r/20221123121911.3446224-3-vsujithkumar.reddy@amd.corp-partner.google.com Signed-off-by: Mark Brown --- sound/soc/sof/amd/acp.c | 4 +++- sound/soc/sof/amd/acp.h | 8 ++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c index 36966643e36ab..47115a77c92cc 100644 --- a/sound/soc/sof/amd/acp.c +++ b/sound/soc/sof/amd/acp.c @@ -390,6 +390,7 @@ static int acp_power_on(struct snd_sof_dev *sdev) static int acp_reset(struct snd_sof_dev *sdev) { + const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); unsigned int val; int ret; @@ -410,6 +411,7 @@ static int acp_reset(struct snd_sof_dev *sdev) if (ret < 0) dev_err(sdev->dev, "timeout in releasing reset\n"); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); return ret; } @@ -456,7 +458,7 @@ int amd_sof_acp_resume(struct snd_sof_dev *sdev) return ret; } - snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, 0x03); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); ret = acp_memory_init(sdev); diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h index 1529c6d9bf9b9..76ad963faec1e 100644 --- a/sound/soc/sof/amd/acp.h +++ b/sound/soc/sof/amd/acp.h @@ -69,6 +69,14 @@ #define BOX_SIZE_512 0x200 #define BOX_SIZE_1024 0x400 +enum clock_source { + ACP_CLOCK_96M = 0, + ACP_CLOCK_48M, + ACP_CLOCK_24M, + ACP_CLOCK_ACLK, + ACP_CLOCK_MCLK, +}; + struct acp_atu_grp_pte { u32 low; u32 high; -- 2.50.1