From dc79d3d5e7c7b2c177b4a4ca84d20d271fb68da0 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Mon, 10 Mar 2025 18:41:13 +0800 Subject: [PATCH] arm64: dts: rockchip: Add eDP0 node for RK3588 Add support for the eDP0 output on RK3588 SoC. Signed-off-by: Damon Ding Link: https://lore.kernel.org/r/20250310104114.2608063-13-damon.ding@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 4e3c28d99459..064235253dab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1453,6 +1453,34 @@ }; }; + edp0: edp@fdec0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfdec0000 0x0 0x1000>; + clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>; + clock-names = "dp", "pclk"; + interrupts = ; + phys = <&hdptxphy0>; + phy-names = "dp"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; + reset-names = "dp", "apb"; + rockchip,grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp0_in: port@0 { + reg = <0>; + }; + + edp0_out: port@1 { + reg = <1>; + }; + }; + }; + qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>; -- 2.50.1