From d32c49e318df0a3f334c2d2ff95ce4600df2d6bf Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Tue, 3 Oct 2023 13:16:28 -0700 Subject: [PATCH] drm/xe: Fix devcoredump readout of IPEHR MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit It was reading (base) + 0x8c but that is not a valid register and instead it should read (base) + 0x68. So here reading the correct register and removing the wrong and duplicated. Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/regs/xe_engine_regs.h | 1 - drivers/gpu/drm/xe/xe_hw_engine.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h index 692213d09cea..792d431161c6 100644 --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h @@ -37,7 +37,6 @@ #define RING_DMA_FADD(base) XE_REG((base) + 0x78) #define RING_HWS_PGA(base) XE_REG((base) + 0x80) #define IPEIR(base) XE_REG((base) + 0x88) -#define IPEHR(base) XE_REG((base) + 0x8c) #define RING_HWSTAM(base) XE_REG((base) + 0x98) #define RING_MI_MODE(base) XE_REG((base) + 0x9c) #define RING_NOPID(base) XE_REG((base) + 0x94) diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index dc9dd83d99c5..c2db391cf267 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -728,7 +728,7 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe) snapshot->reg.ring_dma_fadd = hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)); snapshot->reg.ipeir = hw_engine_mmio_read32(hwe, IPEIR(0)); - snapshot->reg.ipehr = hw_engine_mmio_read32(hwe, IPEHR(0)); + snapshot->reg.ipehr = hw_engine_mmio_read32(hwe, RING_IPEHR(0)); if (snapshot->class == XE_ENGINE_CLASS_COMPUTE) snapshot->reg.rcu_mode = xe_mmio_read32(hwe->gt, RCU_MODE); -- 2.50.1