From cee7bef61f51c04c9946cf4ddb81e85d9c1833d2 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Mon, 22 Jan 2024 13:11:14 +0200 Subject: [PATCH] arm64: dts: renesas: r9a08g045: Add watchdog node Add the DT node for the watchdog IP accessible by Cortex-A of RZ/G3S SoC (R9108G045). Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240122111115.2861835-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 5facfad96158..dfee878c0f49 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -264,6 +264,20 @@ <0x0 0x12440000 0 0x60000>; interrupts = ; }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>, + <&cpg CPG_MOD R9A08G045_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A08G045_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer { -- 2.50.1