From cd81339e68cb11dbec90fd0d7de12a5c307c1fc7 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 12 May 2025 13:54:44 -0700 Subject: [PATCH] arm64: dts: qcom: sm8750: Add LLCC node Add LLCC node for SM8750 SoC. Signed-off-by: Melody Olvera Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250512-sm8750_llcc_master-v5-4-d78dca6282a5@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 149d2ed17641..980ba1ca23c4 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3402,6 +3402,24 @@ #interconnect-cells = <2>; }; + system-cache-controller@24800000 { + compatible = "qcom,sm8750-llcc"; + reg = <0x0 0x24800000 0x0 0x200000>, + <0x0 0x25800000 0x0 0x200000>, + <0x0 0x24c00000 0x0 0x200000>, + <0x0 0x25c00000 0x0 0x200000>, + <0x0 0x26800000 0x0 0x200000>, + <0x0 0x26c00000 0x0 0x200000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts = ; + }; + nsp_noc: interconnect@320c0000 { compatible = "qcom,sm8750-nsp-noc"; reg = <0x0 0x320c0000 0x0 0x13080>; -- 2.50.1