From cce581a0c3bed56252996112cda5652d90d9c028 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ren=C3=A9=20van=20Dorst?= Date: Sat, 29 Jun 2019 14:24:51 +0200 Subject: [PATCH] net: ethernet: mediatek: Allow non TRGMII mode with MT7621 DDR2 devices MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit No reason to error out on a MT7621 device with DDR2 memory when non TRGMII mode is selected. Only MT7621 DDR2 clock setup is not supported for TRGMII mode. But non TRGMII mode doesn't need any special clock setup. Signed-off-by: René van Dorst Signed-off-by: David S. Miller --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 066712f2e985..b20b3a5a1ebb 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -139,9 +139,12 @@ static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, { u32 val; - /* Check DDR memory type. Currently DDR2 is not supported. */ + /* Check DDR memory type. + * Currently TRGMII mode with DDR2 memory is not supported. + */ regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); - if (val & SYSCFG_DRAM_TYPE_DDR2) { + if (interface == PHY_INTERFACE_MODE_TRGMII && + val & SYSCFG_DRAM_TYPE_DDR2) { dev_err(eth->dev, "TRGMII mode with DDR2 memory is not supported!\n"); return -EOPNOTSUPP; -- 2.49.0