From ccd015b02d18e708bfebe41f017634b88903f057 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 23 Jan 2025 12:01:57 +0100 Subject: [PATCH] MIPS: CPS: Support broken HCI for multicluster Some CM3.5 devices incorrectly report that hardware cache initialization has completed, and also claim to support hardware cache initialization when they don't actually do so. This commit fixes this issue by retrieving the correct information from the device tree and allowing the system to bypass the hardware cache initialization step. Instead, it relies on manual operation. As a result, multi-user support is now possible for these CPUs. Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/smp-cps.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index b20ea4048429..e85bd087467e 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -333,6 +333,9 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) sizeof(*mips_cps_cluster_bootcfg), GFP_KERNEL); + if (nclusters > 1) + mips_cm_update_property(); + for (cl = 0; cl < nclusters; cl++) { /* Allocate core boot configuration structs */ ncores = mips_cps_numcores(cl); @@ -394,7 +397,7 @@ static void init_cluster_l2(void) { u32 l2_cfg, l2sm_cop, result; - while (1) { + while (!mips_cm_is_l2_hci_broken) { l2_cfg = read_gcr_redir_l2_ram_config(); /* If HCI is not supported, use the state machine below */ -- 2.50.1