From cc9d29aad876d83e752a1da6dc978088b248427e Mon Sep 17 00:00:00 2001 From: Yuvaraj Ranganathan Date: Mon, 25 Nov 2024 12:28:01 +0530 Subject: [PATCH] arm64: dts: qcom: qcs8300: enable the inline crypto engine Add an ICE node to qcs8300 SoC description and enable it by adding a phandle to the UFS node. Signed-off-by: Yuvaraj Ranganathan Link: https://lore.kernel.org/r/20241125065801.1751256-3-quic_yrangana@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 9f67ef26ac3d..35380ef738b9 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -717,6 +717,7 @@ <0 0>, <0 0>, <0 0>; + qcom,ice = <&ice>; status = "disabled"; }; @@ -767,6 +768,13 @@ interconnect-names = "memory"; }; + ice: crypto@1d88000 { + compatible = "qcom,qcs8300-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x18000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; -- 2.50.1