From b7bc69b90736a281490d535c6786b6c23c1b22e8 Mon Sep 17 00:00:00 2001 From: Felix Kaechele Date: Sun, 6 Apr 2025 15:52:02 +0200 Subject: [PATCH] arm64: dts: qcom: msm8953: Add uart_5 Add the node and pinctrl for uart_5 found on the MSM8953 SoC. Signed-off-by: Felix Kaechele [luca: Prepare patch for upstream submission] Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250406-msm8953-uart_5-v1-1-7e4841674137@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 28fef68f7348..d18a59238535 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -768,6 +768,20 @@ bias-disable; }; + uart_5_default: uart-5-default-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "blsp_uart5"; + drive-strength = <16>; + bias-disable; + }; + + uart_5_sleep: uart-5-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wcnss_pin_a: wcnss-active-state { wcss-wlan2-pins { @@ -1593,6 +1607,24 @@ qcom,controlled-remotely; }; + uart_5: serial@7aef000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x07aef000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&uart_5_default>; + pinctrl-1 = <&uart_5_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + }; + i2c_5: i2c@7af5000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07af5000 0x600>; -- 2.50.1