From b1e157c61db5e6f8d9c35e8ebc714ab6ce02ee41 Mon Sep 17 00:00:00 2001 From: =?utf8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Mon, 21 Apr 2025 16:49:07 -0400 Subject: [PATCH] arm64: dts: mediatek: mt8188: Describe SCP as a cluster with two cores MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The SCP is currently described in the Devicetree as a single-core processor, but really it is a cluster with two cores. Describe the full cluster but enable only core0 on the current mt8188 platforms since that's the only one usable with the upstream firmware. Co-developed-by: Tinghan Shen Signed-off-by: Tinghan Shen Co-developed-by: Jason Chen Signed-off-by: Jason Chen Signed-off-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20250421-scp-dual-core-mt8390-v2-4-c84117a959a9@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188-evb.dts | 6 +++- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 36 ++++++++++++++----- .../dts/mediatek/mt8390-genio-common.dtsi | 6 +++- 3 files changed, 37 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188-evb.dts b/arch/arm64/boot/dts/mediatek/mt8188-evb.dts index f89835ac36f3..f4c207d65b87 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8188-evb.dts @@ -331,7 +331,11 @@ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; -&scp { +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { memory-region = <&scp_mem_reserved>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 0cfedb837b00..296090fbaf49 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1382,12 +1382,30 @@ clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; }; - scp: scp@10500000 { - compatible = "mediatek,mt8188-scp"; - reg = <0 0x10500000 0 0x100000>, - <0 0x10720000 0 0xe0000>; - reg-names = "sram", "cfg"; - interrupts = ; + scp_cluster: scp@10720000 { + compatible = "mediatek,mt8188-scp-dual"; + reg = <0 0x10720000 0 0xe0000>; + reg-names = "cfg"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x10500000 0x100000>; + status = "disabled"; + + scp_c0: scp@0 { + compatible = "mediatek,scp-core"; + reg = <0x0 0xd0000>; + reg-names = "sram"; + interrupts = ; + status = "disabled"; + }; + + scp_c1: scp@d0000 { + compatible = "mediatek,scp-core"; + reg = <0xd0000 0x2f000>; + reg-names = "sram"; + interrupts = ; + status = "disabled"; + }; }; afe: audio-controller@10b10000 { @@ -2249,7 +2267,7 @@ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; mediatek,gce-events = , ; - mediatek,scp = <&scp>; + mediatek,scp = <&scp_c0>; }; display@14002000 { @@ -2704,7 +2722,7 @@ iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; #address-cells = <2>; #size-cells = <2>; - mediatek,scp = <&scp>; + mediatek,scp = <&scp_c0>; video-codec@10000 { compatible = "mediatek,mtk-vcodec-lat"; @@ -2828,7 +2846,7 @@ <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; - mediatek,scp = <&scp>; + mediatek,scp = <&scp_c0>; }; jpeg_encoder: jpeg-encoder@1a030000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index e9d57f44475b..805a4bccff33 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -1055,7 +1055,11 @@ }; }; -&scp { +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { memory-region = <&scp_mem>; status = "okay"; }; -- 2.50.1