From b1ae6881fbe3e86f74c2edb8c02681af6ab110b7 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 May 2025 09:47:53 -0500 Subject: [PATCH] dt-bindings: interrupt-controller: Convert microchip,pic32mzda-evic to DT schema Convert the Microchip PIC32 interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250505144754.1291072-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../microchip,pic32-evic.txt | 67 ------------------- .../microchip,pic32mzda-evic.yaml | 60 +++++++++++++++++ 2 files changed, 60 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt deleted file mode 100644 index c3a1b37c4c358..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt +++ /dev/null @@ -1,67 +0,0 @@ -Microchip PIC32 Interrupt Controller -==================================== - -The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC). -It handles all internal and external interrupts. This controller exists outside -of the CPU and is the arbitrator of all interrupts (including interrupts from -the CPU itself) before they are presented to the CPU. - -External interrupts have a software configurable edge polarity. Non external -interrupts have a type and polarity that is determined by the source of the -interrupt. - -Required properties -------------------- - -- compatible: Should be "microchip,pic32mzda-evic" -- reg: Specifies physical base address and size of register range. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt cells: Specifies the number of cells used to encode an interrupt - source connected to this controller. The value shall be 2 and interrupt - descriptor shall have the following format: - - - - hw_irq - represents the hardware interrupt number as in the data sheet. - irq_type - is used to describe the type and polarity of an interrupt. For - internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and - IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use - IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity. - -Optional properties -------------------- -- microchip,external-irqs: u32 array of external interrupts with software - polarity configuration. This array corresponds to the bits in the INTCON - SFR. - -Example -------- - -evic: interrupt-controller@1f810000 { - compatible = "microchip,pic32mzda-evic"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1f810000 0x1000>; - microchip,external-irqs = <3 8 13 18 23>; -}; - -Each device/peripheral must request its interrupt line with the associated type -and polarity. - -Internal interrupt DTS snippet ------------------------------- - -device@1f800000 { - ... - interrupts = <113 IRQ_TYPE_LEVEL_HIGH>; - ... -}; - -External interrupt DTS snippet ------------------------------- - -device@1f800000 { - ... - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - ... -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml new file mode 100644 index 0000000000000..74bfc42693f08 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/microchip,pic32mzda-evic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32 EVIC Interrupt Controller + +maintainers: + - Cristian Birsan + +description: > + The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC). + It handles all internal and external interrupts. This controller exists + outside of the CPU and is the arbitrator of all interrupts (including + interrupts from the CPU itself) before they are presented to the CPU. + + External interrupts have a software configurable edge polarity. Non external + interrupts have a type and polarity that is determined by the source of the + interrupt. + +properties: + compatible: + items: + - const: microchip,pic32mzda-evic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + + microchip,external-irqs: + description: + External interrupts with software polarity configuration corresponding to + the INTCON SFR bits. + $ref: /schemas/types.yaml#/definitions/uint32-array + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@1f810000 { + compatible = "microchip,pic32mzda-evic"; + reg = <0x1f810000 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + microchip,external-irqs = <3 8 13 18 23>; + }; -- 2.50.1