From ad2011e02dab5ccc9f38848a3d909855a4ae7c8f Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Tue, 25 Mar 2025 18:00:18 +0530 Subject: [PATCH] arm64: dts: qcom: qcs615: Add snps,dis_u3_susphy_quirk During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. Signed-off-by: Pratham Pratap Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250325123019.597976-5-prashanth.k@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index edfb796d8dd3..7c377f3402c1 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3600,6 +3600,7 @@ snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; @@ -3661,6 +3662,7 @@ phy-names = "usb2-phy"; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; -- 2.50.1