From ab4999906aed5b97985d47e52f7465358cf920e6 Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Wed, 19 Feb 2025 11:42:25 +0100 Subject: [PATCH] clk: socfpga: clk-pll: Optimize local variables Since readl() returns a u32, the local variables reg and bypass can also have the data type u32. Furthermore, divf and divq are derived from reg and can also be a u32. Since do_div() casts the divisor to u32 anyway, changing the data type of divq to u32 removes the following Coccinelle/coccicheck warning reported by do_div.cocci: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead Compile-tested only. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thorsten Blum Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index 9dcc1b2d2cc0..03a96139a576 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -39,9 +39,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, unsigned long parent_rate) { struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); - unsigned long divf, divq, reg; + u32 divf, divq, reg; unsigned long long vco_freq; - unsigned long bypass; + u32 bypass; reg = readl(socfpgaclk->hw.reg); bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); -- 2.50.1