From a714b31225bce9ce2732f6193f28f371093492f0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 17 Apr 2025 23:23:23 +0000 Subject: [PATCH] ASoC: renesas: rsnd: care BRGA/BRGB select in rsnd_adg_clk_enable() Renesas rsnd related clocks are enabled by rsnd_adg_clk_enable(), but it doesn't care about BRGA/BRGB selection (It is handled when SSI was started) (BRGA is used for 44.1kHz lineage, BRGB is used for 48kHz lineage in this driver). But it should be handled since probe time. Includes BRGCKR_31 in adg->ckr to handle it since boot time. Signed-off-by: Kuninori Morimoto Link: https://patch.msgid.link/87tt6m2x05.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown --- sound/soc/renesas/rcar/adg.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/sound/soc/renesas/rcar/adg.c b/sound/soc/renesas/rcar/adg.c index 191f212d338c..e6b7273b27ad 100644 --- a/sound/soc/renesas/rcar/adg.c +++ b/sound/soc/renesas/rcar/adg.c @@ -19,6 +19,7 @@ #define CLKOUT3 3 #define CLKOUTMAX 4 +#define BRGCKR_31 (1 << 31) #define BRRx_MASK(x) (0x3FF & x) static struct rsnd_mod_ops adg_ops = { @@ -361,10 +362,13 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) rsnd_adg_set_ssi_clk(ssi_mod, data); + ckr = adg->ckr & ~BRGCKR_31; if (0 == (rate % 8000)) - ckr = 0x80000000; /* BRGB output = 48kHz */ - - rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr); + ckr |= BRGCKR_31; /* use BRGB output = 48kHz */ + if (ckr != adg->ckr) { + rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr); + adg->ckr = ckr; + } dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n", (ckr) ? 'B' : 'A', @@ -683,6 +687,9 @@ static int rsnd_adg_get_clkout(struct rsnd_priv *priv) } rsnd_adg_get_clkout_end: + if (0 == (req_rate[0] % 8000)) + ckr |= BRGCKR_31; /* use BRGB output = 48kHz */ + adg->ckr = ckr; adg->brga = brga; adg->brgb = brgb; -- 2.50.1