From a6f59c0445540f07bef226b33c999f2e63c6dfa2 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 11 Sep 2024 20:35:39 -0400 Subject: [PATCH] drm/amd/display: correct register Clock Gater incorrectly disabled [why] The "dpp35_dppclk_control" routine is incorrectly disabling the register clock gater when the DPP is enabled. The "DISPCLK_R_GATE_DISABLE" should never be set to 1 in the normal operating mode. This will disable the clock gater and the DPPCLK register clock branch will always be running. As a consequence, the dynamic power will be higher than expected. Reviewed-by: Alvin Lee Signed-off-by: Charlene Liu Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c index 8473c694bfdc..9f885a03eec6 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c @@ -50,13 +50,11 @@ void dpp35_dppclk_control( DPPCLK_RATE_CONTROL, dppclk_div, DPP_CLOCK_ENABLE, 1); else - REG_UPDATE_2(DPP_CONTROL, - DPP_CLOCK_ENABLE, 1, - DISPCLK_R_GATE_DISABLE, 1); + REG_UPDATE(DPP_CONTROL, + DPP_CLOCK_ENABLE, 1); } else - REG_UPDATE_2(DPP_CONTROL, - DPP_CLOCK_ENABLE, 0, - DISPCLK_R_GATE_DISABLE, 0); + REG_UPDATE(DPP_CONTROL, + DPP_CLOCK_ENABLE, 0); } void dpp35_program_bias_and_scale_fcnv( -- 2.50.1