From 9c4cd0aef259d41355f90e0dbb2d3574f3830de9 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 9 Oct 2024 18:17:15 +0200 Subject: [PATCH] arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS). Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. This specifically allows NVMe and Wi-Fi interrupts to be processed on all cores (and not just on CPU0). Note that using the GIC ITS on x1e80100 will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. Consequently, notifications about (correctable) errors may now be logged for errors that previously went unnoticed. Also note that PCIe5 (and PCIe3) can currently only be used with the internal MSI controller due to a platform (firmware) limitation. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20241009161715.14994-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 182142b92671..75c850f583b7 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2934,6 +2934,8 @@ linux,pci-domain = <6>; num-lanes = <2>; + msi-map = <0x0 &gic_its 0xe0000 0x10000>; + interrupts = , , , @@ -3176,6 +3178,8 @@ linux,pci-domain = <4>; num-lanes = <2>; + msi-map = <0x0 &gic_its 0xc0000 0x10000>; + interrupts = , , , @@ -5766,8 +5770,6 @@ msi-controller; #msi-cells = <1>; - - status = "disabled"; }; }; -- 2.50.1