From 97b05c8c2e1e0390f4447dc9cc5ec131dd54ca02 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Fri, 24 Jan 2025 09:59:37 -0500 Subject: [PATCH] drm/amd/display: Apply DCN35 DML2 state policy for DCN36 too [Why] DCN36 should inherit the same policy as DCN35 for DML2. [How] Add it to the list of checks in translation helper. Signed-off-by: Nicholas Kazlauskas Reviewed-by: Zaeem Mohamed Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c index f829d5ac7c8e..2061d43b92e1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c @@ -557,6 +557,7 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, } if (dml2->v20.dml_core_ctx.project == dml_project_dcn35 || + dml2->v20.dml_core_ctx.project == dml_project_dcn36 || dml2->v20.dml_core_ctx.project == dml_project_dcn351) { int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0, max_socclk_mhz = 0; -- 2.50.1