From 87545d7584e12651c6b54f50f3287104205f8dc6 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 6 Nov 2024 23:58:56 +0200 Subject: [PATCH] drm/i915/pps: Spell out the eDP spec power sequencing delays a bit more clearly MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit We determine the "spec" eDP power sequencing delays by referencing some max values from the eDP spec. Write out each number from the spec explicitly instead of precomputing the final number (that's the job of the computer). Makes it a bit easier to see what the supposed spec defined numbers actually are. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20241106215859.25446-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pps.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index ed52f84d4cf3..6946ba0004eb 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1512,11 +1512,11 @@ static void pps_init_delays_spec(struct intel_dp *intel_dp, /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of * our hw here, which are all in 100usec. */ - spec->power_up = 210 * 10; /* T1+T3 */ + spec->power_up = (10 + 200) * 10; /* T1+T3 */ spec->backlight_on = 50 * 10; /* no limit for T8, use T7 instead */ spec->backlight_off = 50 * 10; /* no limit for T9, make it symmetric with T8 */ spec->power_down = 500 * 10; /* T10 */ - spec->power_cycle = 510 * 10; /* T11+T12 */ + spec->power_cycle = (10 + 500) * 10; /* T11+T12 */ intel_pps_dump_state(intel_dp, "spec", spec); } -- 2.50.1