From 85582ad0bc44960def44c78674c0c9b8dc007817 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jouni=20H=C3=B6gander?= Date: Wed, 19 Jun 2024 09:21:31 +0300 Subject: [PATCH] drm/i915/psr: Modify dg2_activate_panel_replay to support eDP MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit There are couple of bits in PSR2_CTL which needs to be written in case of eDP Panel Replay Bspec: 68920 v2: use boolean instead of assuming eDP Panel Replay mean Early Transport Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-12-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index d40715d4b5d5..9cb1cdaaeefa 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -951,6 +951,19 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp) static void dg2_activate_panel_replay(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_psr *psr = &intel_dp->psr; + enum transcoder cpu_transcoder = intel_dp->psr.transcoder; + + if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { + u32 val = psr->su_region_et_enabled ? + LNL_EDP_PSR2_SU_REGION_ET_ENABLE : 0; + + if (intel_dp->psr.req_psr2_sdp_prior_scanline) + val |= EDP_PSR2_SU_SDP_SCANLINE; + + intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder), + val); + } intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(dev_priv, intel_dp->psr.transcoder), -- 2.50.1