From 7abe72765d9f6a900a1c2b6c12b9dd70010a8b0b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 19 Sep 2024 00:57:20 +0200 Subject: [PATCH] arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio Tested-by: Luca Weiss # sm7225-fairphone-fp4 Tested-by: Steev Klimaszewski # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-7-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 7986ddb30f6e..54cfe9900661 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2685,6 +2685,7 @@ , , ; + dma-coherent; }; intc: interrupt-controller@17a00000 { -- 2.50.1