From 5207d9c75f18db46ce42074f6585c7ca8e4aca75 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 19 Sep 2024 00:57:24 +0200 Subject: [PATCH] arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio Tested-by: Steev Klimaszewski # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-11-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index a36076e3c56b..d364d5ebdaaf 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5738,6 +5738,8 @@ #iommu-cells = <2>; #global-interrupts = <1>; + + dma-coherent; }; intc: interrupt-controller@17000000 { -- 2.50.1