From 4e7ad3b4464571d7bec6869944151b27cce44435 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 2 Apr 2025 17:02:01 +0530 Subject: [PATCH] arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis [j-choudhary@ti.com: Add changes to k3-am642-evm-pcie0-ep.dtso] Signed-off-by: Jayesh Choudhary Reviewed-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250402113201.151195-6-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++++- arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 324eb44c258d3..d872a624601cb 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -51,6 +51,11 @@ reg = <0x00000014 0x4>; }; + pcie0_ctrl: pcie-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x4>; @@ -1036,7 +1041,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; max-link-speed = <2>; num-lanes = <1>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso index 6b029539e0dbb..4327517748534 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso @@ -46,6 +46,6 @@ max-functions = /bits/ 8 <1>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; - ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; }; }; -- 2.50.1