From 3b3c9e865e1d7c1c926ea768a03d01997c991ede Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 3 May 2024 12:28:01 +0530 Subject: [PATCH] drm/amdgpu: add se registers to ip dump for gfx10 add the registers of SE block of gfx for ip dump for gfx10 IP. Signed-off-by: Sunil Khatri Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 61c1e997f794..953df202953a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -373,7 +373,12 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = { SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP), SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP) + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP), + /* SE status registers */ + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0), + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1), + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2), + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) }; static const struct soc15_reg_golden golden_settings_gc_10_1[] = { -- 2.50.1