From 3620328f787de5190c3c7b0b0041348dc11d796a Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Tue, 9 Nov 2021 16:29:11 -0300 Subject: [PATCH] target/ppc: Fix register update on lf[sd]u[x]/stf[sd]u[x] MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit These instructions should update the GPR indicated by the field RA instead of RT. This error caused a regression on Mac OS 9 boot and some graphical glitches in OS X. Fixes: a39a106634a9 ("target/ppc: Move load and store floating point instructions to decodetree") Reported-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland Signed-off-by: Matheus Ferst Signed-off-by: Cédric Le Goater --- target/ppc/translate/fp-impl.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index d1dbb1b96b..c9e05201d9 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -1328,7 +1328,7 @@ static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ, set_fpr(rt, t0); } if (update) { - tcg_gen_mov_tl(cpu_gpr[rt], ea); + tcg_gen_mov_tl(cpu_gpr[ra], ea); } tcg_temp_free_i64(t0); tcg_temp_free(ea); -- 2.49.0