From 34b69113ab975e8718b24b9b2cd4b1ea8dc107d8 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Mon, 14 Apr 2025 20:37:38 +0200 Subject: [PATCH] arm64: dts: rockchip: enable pcie on Sige5 The ArmSoM Sige5 board exposes PCIe controller 0 on its M.2 slot on the bottom of the board. Enable the necessary nodes for it, and also add the correct pins for both the power enable GPIO and the PCIe reset GPIO. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250414-rk3576-sige5-pcie-v1-1-0e950a96f392@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-armsom-sige5.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 828bde7fab68..964ee351d3b6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -117,6 +117,8 @@ vcc_3v3_pcie: regulator-vcc-3v3-pcie { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; regulator-name = "vcc_3v3_pcie"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -177,6 +179,10 @@ }; }; +&combphy0_ps { + status = "okay"; +}; + &cpu_l0 { cpu-supply = <&vdd_cpu_lit_s0>; }; @@ -634,6 +640,14 @@ }; }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie>; + status = "okay"; +}; + &pinctrl { headphone { hp_det: hp-det { @@ -655,6 +669,15 @@ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + pcie_reset: pcie-reset { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; }; &sdhci { -- 2.50.1