From 320f7a476c5fe79f50d00c75debfd9f63a0e713f Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 28 Oct 2024 19:48:19 +0100 Subject: [PATCH] clk: qcom: dispcc-sm6115: remove alpha values from disp_cc_pll0_config Since both the 'alpha' and 'alpha_hi' members of the configuration is initialized (the latter is implicitly) with zero values, the output rate of the PLL will be the same whether alpha mode is enabled or not. Remove the initialization of the alpha* members to make it clear that the alpha mode is not required to get the desired output rate. Despite that enabling alpha mode is not needed for the initial configuration, the set_rate() op might require that it is enabled already. In this particular case however, the clk_alpha_pll_set_rate() function will get reset the ALPHA_EN bit when the PLL's rate changes, so dropping 'alpha_en_mask' is safe. No functional changes intended, compile tested only. Reviewed-by: Dmitry Baryshkov Signed-off-by: Gabor Juhos Link: https://lore.kernel.org/r/20241028-alpha-mode-cleanup-v2-5-9bc6d712bd76@gmail.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/dispcc-sm6115.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c index 939887f82ecc..2b236d52b29f 100644 --- a/drivers/clk/qcom/dispcc-sm6115.c +++ b/drivers/clk/qcom/dispcc-sm6115.c @@ -48,8 +48,6 @@ static const struct pll_vco spark_vco[] = { /* 768MHz configuration */ static const struct alpha_pll_config disp_cc_pll0_config = { .l = 0x28, - .alpha = 0x0, - .alpha_en_mask = BIT(24), .vco_val = 0x2 << 20, .vco_mask = GENMASK(21, 20), .main_output_mask = BIT(0), -- 2.50.1