From 2eb0e67ef063835b3fa5a8b8feaf6beae024b060 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 14 Apr 2025 14:29:43 +0300 Subject: [PATCH] drm/i915: use 32-bit access for gen2 irq registers MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit We've previously switched from 16-bit to 32-bit access for gen2 irq registers, but one was left behind. Fix it. Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/5a56286c94e08a02435c60ce0fbff13aca6c0d1f.1744630147.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_gpu_error.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 819ab933bb10..df16c2b86b9d 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1782,8 +1782,6 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt) gt->ier = intel_uncore_read(uncore, VLV_IER); else if (HAS_PCH_SPLIT(i915)) gt->ier = intel_uncore_read(uncore, DEIER); - else if (GRAPHICS_VER(i915) == 2) - gt->ier = intel_uncore_read16(uncore, GEN2_IER); else gt->ier = intel_uncore_read(uncore, GEN2_IER); } -- 2.50.1