From 2a4067c89e4137c477ca6f367e65ace0f2132922 Mon Sep 17 00:00:00 2001 From: Shin Son Date: Wed, 23 Apr 2025 13:41:53 +0900 Subject: [PATCH] arm64: dts: exynosautov920: add cpucl0 clock DT nodes Add cmu_cpucl0 clocks for switch, cluster, and dbg domains respectively. Signed-off-by: Shin Son Link: https://lore.kernel.org/r/20250423044153.1288077-4-shin.son@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index c1b7d05d30da..9350c53f935e 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1075,6 +1075,21 @@ compatible = "samsung,exynosautov920-pinctrl"; reg = <0x1a460000 0x10000>; }; + + cmu_cpucl0: clock-controller@1ec00000 { + compatible = "samsung,exynosautov920-cmu-cpucl0"; + reg = <0x1ec00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_CPUCL0_SWITCH>, + <&cmu_top DOUT_CLKCMU_CPUCL0_CLUSTER>, + <&cmu_top DOUT_CLKCMU_CPUCL0_DBG>; + clock-names = "oscclk", + "switch", + "cluster", + "dbg"; + }; }; timer { -- 2.50.1