From 24816cc298ee9cc01003b10b888427faada4403d Mon Sep 17 00:00:00 2001 From: Jon Pan-Doh Date: Thu, 22 May 2025 18:21:25 -0500 Subject: [PATCH] PCI/AER: Add ratelimits to PCI AER Documentation MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Add ratelimits section for rationale and defaults. [bhelgaas: note fatal errors are not ratelimited] Signed-off-by: Karolina Stolarek Signed-off-by: Jon Pan-Doh Signed-off-by: Bjorn Helgaas Tested-by: Krzysztof Wilczyński Reviewed-by: Kuppuswamy Sathyanarayanan Acked-by: Paul E. McKenney Link: https://patch.msgid.link/20250522232339.1525671-20-helgaas@kernel.org --- Documentation/PCI/pcieaer-howto.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/PCI/pcieaer-howto.rst b/Documentation/PCI/pcieaer-howto.rst index f013f3b27c82..6fb31516fff1 100644 --- a/Documentation/PCI/pcieaer-howto.rst +++ b/Documentation/PCI/pcieaer-howto.rst @@ -85,6 +85,18 @@ In the example, 'Requester ID' means the ID of the device that sent the error message to the Root Port. Please refer to PCIe specs for other fields. +AER Ratelimits +-------------- + +Since error messages can be generated for each transaction, we may see +large volumes of errors reported. To prevent spammy devices from flooding +the console/stalling execution, messages are throttled by device and error +type (correctable vs. non-fatal uncorrectable). Fatal errors, including +DPC errors, are not ratelimited. + +AER uses the default ratelimit of DEFAULT_RATELIMIT_BURST (10 events) over +DEFAULT_RATELIMIT_INTERVAL (5 seconds). + AER Statistics / Counters ------------------------- -- 2.50.1