From 22f2d8bb1d1065dede59b73b148ad4b4e2177c33 Mon Sep 17 00:00:00 2001 From: Pu Wen Date: Thu, 23 May 2019 21:00:22 +0800 Subject: [PATCH] ras-mce-handler: Add support for Hygon Dhyana family 18h processor The Hygon Dhyana family 18h processor is derived from AMD family 17h. The Hygon Dhyana support to Linux is already accepted upstream[1]. Add Hygon Dhyana support to mce handler of rasdaemon in order to handle MCE events on Hygon Dhyana platforms. Reference: [1] https://git.kernel.org/tip/fec98069fb72fb656304a3e52265e0c2fc9adf87 Signed-off-by: Pu Wen Signed-off-by: Mauro Carvalho Chehab --- ras-mce-handler.c | 9 ++++++++- ras-mce-handler.h | 1 + 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/ras-mce-handler.c b/ras-mce-handler.c index 7ab2335..fd3ef3b 100644 --- a/ras-mce-handler.c +++ b/ras-mce-handler.c @@ -55,7 +55,8 @@ static char *cputype_name[] = { [CPU_KNIGHTS_LANDING] = "Knights Landing", [CPU_KNIGHTS_MILL] = "Knights Mill", [CPU_SKYLAKE_XEON] = "Skylake server", - [CPU_NAPLES] = "AMD Family 17h Zen1" + [CPU_NAPLES] = "AMD Family 17h Zen1", + [CPU_DHYANA] = "Hygon Family 18h Moksha" }; static enum cputype select_intel_cputype(struct ras_events *ras) @@ -200,6 +201,11 @@ static int detect_cpu(struct ras_events *ras) ret = EINVAL; } goto ret; + } else if (!strcmp(mce->vendor,"HygonGenuine")) { + if (mce->family == 24) { + mce->cputype = CPU_DHYANA; + } + goto ret; } else if (!strcmp(mce->vendor,"GenuineIntel")) { mce->cputype = select_intel_cputype(ras); } else { @@ -436,6 +442,7 @@ int ras_mce_event_handler(struct trace_seq *s, rc = parse_amd_k8_event(ras, &e); break; case CPU_NAPLES: + case CPU_DHYANA: rc = parse_amd_smca_event(ras, &e); break; default: /* All other CPU types are Intel */ diff --git a/ras-mce-handler.h b/ras-mce-handler.h index 8aaecd1..94395eb 100644 --- a/ras-mce-handler.h +++ b/ras-mce-handler.h @@ -51,6 +51,7 @@ enum cputype { CPU_KNIGHTS_MILL, CPU_SKYLAKE_XEON, CPU_NAPLES, + CPU_DHYANA, }; struct mce_event { -- 2.50.1