From 1f326fb84a6074772f01dc63ed4d3eb791682479 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 2 Apr 2025 17:01:59 +0530 Subject: [PATCH] arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis [j-choudhary@ti.com: Add changes to k3-j7200-evm-pcie1-ep.dtso] Signed-off-by: Jayesh Choudhary Reviewed-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250402113201.151195-4-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso index 3cc315a0e084..281076d905f3 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso @@ -48,6 +48,6 @@ dma-coherent; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 5ab510a0605f..dbb000657377 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -32,6 +32,11 @@ #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + pcie1_ctrl: pcie-ctrl@4074 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4074 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x20>; @@ -764,7 +769,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; -- 2.50.1