From 1a46f7842e4744150dea06a63d1e0251b791b0fa Mon Sep 17 00:00:00 2001
From: Mauro Carvalho Chehab <mchehab@redhat.com>
Date: Sat, 18 May 2013 11:20:37 -0300
Subject: [PATCH] Add a parser for Intel P4/P6 specific CPU error messages

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
---
 Makefile.am                            |  2 +-
 mce-intel-core2.c => mce-intel-p4-p6.c | 28 ++++++++++++++++++++++++--
 mce-intel.c                            |  8 ++------
 ras-mce-handler.h                      |  1 +
 4 files changed, 30 insertions(+), 9 deletions(-)
 rename mce-intel-core2.c => mce-intel-p4-p6.c (85%)

diff --git a/Makefile.am b/Makefile.am
index 5705298..54ac345 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -12,7 +12,7 @@ if WITH_AER
 endif
 if WITH_MCE
    rasdaemon_SOURCES += ras-mce-handler.c mce-intel.c mce-amd-k8.c \
-			bitfield.c mce-intel-core2.c
+			bitfield.c mce-intel-p4-p6.c
 endif
 rasdaemon_LDADD = -lpthread $(SQLITE3_LIBS) libtrace/libtrace.a
 
diff --git a/mce-intel-core2.c b/mce-intel-p4-p6.c
similarity index 85%
rename from mce-intel-core2.c
rename to mce-intel-p4-p6.c
index 0403afe..c8e219d 100644
--- a/mce-intel-core2.c
+++ b/mce-intel-p4-p6.c
@@ -23,8 +23,7 @@
 #include "ras-mce-handler.h"
 #include "bitfield.h"
 
-/* Decode P6 family (Core2) model specific errors.
-   The generic errors are decoded in p4.c */
+/* Decode P4 and P6 family (p6old and Core2) model specific errors */
 
 /* [19..24] */
 static char *bus_queue_req_type[] = {
@@ -107,6 +106,31 @@ static struct numfield p6old_status_numbers[] = {
 	{}
 };
 
+static struct {
+	int value;
+	char *str;
+} p4_model []= {
+	{16, "FSB address parity"},
+	{17, "Response hard fail"},
+	{18, "Response parity"},
+	{19, "PIC and FSB data parity"},
+	{20, "Invalid PIC request(Signature=0xF04H)"},
+	{21, "Pad state machine"},
+	{22, "Pad strobe glitch"},
+	{23, "Pad address glitch"}
+};
+
+void p4_decode_model(struct mce_event *e)
+{
+	uint32_t model = e->status & 0xffff0000L;
+	unsigned i;
+
+	for (i = 0; i < ARRAY_SIZE(p4_model); i++) {
+		if (model & (1 << p4_model[i].value))
+			mce_snprintf(e->error_msg, p4_model[i].str);
+	}
+}
+
 void core2_decode_model(struct mce_event *e)
 {
 	uint64_t status = e->status;
diff --git a/mce-intel.c b/mce-intel.c
index 1fe95db..4bf1a42 100644
--- a/mce-intel.c
+++ b/mce-intel.c
@@ -345,18 +345,14 @@ int parse_intel_event(struct ras_events *ras, struct mce_event *e)
 			break;
 		case CPU_DUNNINGTON:
 		case CPU_CORE2:
+		case CPU_NEHALEM:
+		case CPU_XEON75XX:
 			core2_decode_model(e);
 			break;
-#if 0
 		case CPU_TULSA:
 		case CPU_P4:
 			p4_decode_model(e);
 			break;
-		case CPU_NEHALEM:
-		case CPU_XEON75XX:
-			core2_decode_model(e);
-			break;
-#endif
 		}
 	}
 #if 0
diff --git a/ras-mce-handler.h b/ras-mce-handler.h
index ccf27b0..1789e9d 100644
--- a/ras-mce-handler.h
+++ b/ras-mce-handler.h
@@ -109,6 +109,7 @@ unsigned bitfield_msg(char *buf, size_t len, char **bitarray, unsigned array_len
 		      uint64_t status);
 
 /* Per-CPU-type decoders for Intel CPUs */
+void p4_decode_model(struct mce_event *e);
 void core2_decode_model(struct mce_event *e);
 void p6old_decode_model(struct mce_event *e);
 
-- 
2.50.1