From 1754cea1763e2bdc6a2153220440fe9aa9e0f2c9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 7 Apr 2022 15:46:06 -0400 Subject: [PATCH] drm/amd/display: fix 64 bit divide in freesync code Use div_u64() rather than a a 64 bit divide. Fixes: 3fe5739db48843 ("drm/amd/display: Add flip interval workaround") Reviewed-by: Nathan Chancellor Reported-by: kernel test robot Signed-off-by: Alex Deucher Cc: Angus Wang Cc: Anthony Koo Cc: Aric Cyr Cc: Nathan Chancellor --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 0130f1879116..d2d76ce56f89 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -1239,7 +1239,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, if (in_out_vrr->supported == false) return; - cur_timestamp_in_us = dm_get_timestamp(core_freesync->dc->ctx)/10; + cur_timestamp_in_us = div_u64(dm_get_timestamp(core_freesync->dc->ctx), 10); in_out_vrr->flip_interval.vsyncs_between_flip++; in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us; -- 2.50.1