From 1536dc8edc653e0e4a333035a73ff146d0517749 Mon Sep 17 00:00:00 2001 From: Beniamin Sandu Date: Wed, 15 May 2024 19:12:49 +0100 Subject: [PATCH] arm64: dts: socfpga: stratix10: add L2 cache info This removes cacheinfo warnings at boot, e.g.: cacheinfo: Unable to detect cache hierarchy for CPU 0 Signed-off-by: Beniamin Sandu Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index cbbc53c47921..0def0b0daaf7 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -34,6 +34,7 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x0>; }; @@ -41,6 +42,7 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x1>; }; @@ -48,6 +50,7 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x2>; }; @@ -55,8 +58,15 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x3>; }; + + l2_shared: cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; }; firmware { -- 2.50.1