From 14076e464550053527165aed352c7d9f4bf77e34 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Tue, 18 May 2021 17:06:14 -0700 Subject: [PATCH] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Alderlake-P don't have programing sequences for MBUS or DBUF during display initializaiton, instead it requires programing to those registers during modeset because it to depend on the pipes left enabled. Bspec: 49213 Cc: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper Reviewed-by: Stanislav Lisovskiy Signed-off-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-7-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index e8fcc3d02d01..991ceea06a07 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5245,6 +5245,9 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) { enum dbuf_slice slice; + if (IS_ALDERLAKE_P(dev_priv)) + return; + for_each_dbuf_slice(dev_priv, slice) intel_de_rmw(dev_priv, DBUF_CTL_S(slice), DBUF_TRACKER_STATE_SERVICE_MASK, @@ -5256,6 +5259,9 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask; u32 mask, val, i; + if (IS_ALDERLAKE_P(dev_priv)) + return; + mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | MBUS_ABOX_BT_CREDIT_POOL2_MASK | MBUS_ABOX_B_CREDIT_MASK | -- 2.50.1