]> www.infradead.org Git - users/dwmw2/qemu.git/commit
hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set
authorDaniel Henrique Barboza <dbarboza@ventanamicro.com>
Thu, 6 Jul 2023 10:17:20 +0000 (07:17 -0300)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 10 Jul 2023 12:29:15 +0000 (22:29 +1000)
commit43d1de32f8ef4502005e6b48e6602408fa711390
tree19b53b0c6ec7ae352faa6ce3f57a319a926511af
parenteddabb6b888fa915ed679637983d8f39adfb725c
hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set

The absence of a satp mode in riscv_host_cpu_init() is causing the
following error:

$ ./qemu/build/qemu-system-riscv64  -machine virt,accel=kvm \
    -m 2G -smp 1  -nographic -snapshot \
    -kernel ./guest_imgs/Image \
    -initrd ./guest_imgs/rootfs_kvm_riscv64.img \
    -append "earlycon=sbi root=/dev/ram rw" \
    -cpu host
**
ERROR:../target/riscv/cpu.c:320:satp_mode_str: code should not be
reached
Bail out! ERROR:../target/riscv/cpu.c:320:satp_mode_str: code should
not be reached
Aborted

The error is triggered from create_fdt_socket_cpus() in hw/riscv/virt.c.
It's trying to get satp_mode_str for a NULL cpu->cfg.satp_mode.map.

For this KVM cpu we would need to inherit the satp supported modes
from the RISC-V host. At this moment this is not possible because the
KVM driver does not support it. And even when it does we can't just let
this broken for every other older kernel.

Since mmu-type is not a required node, according to [1], skip the
'mmu-type' FDT node if there's no satp_mode set. We'll revisit this
logic when we can get satp information from KVM.

[1] https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/riscv/cpus.yaml

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230706101738.460804-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/riscv/virt.c