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1 /*

3 *

4 * Permission to use, copy, modify, and/or distribute this software for any

5 * purpose with or without fee is hereby granted, provided that the above

6 * copyright notice and this permission notice appear in all copies.

7 *

8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY

11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION

13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN

14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

15 */

17 #include <linux/delay.h>

18 #include <linux/kernel.h>

19 #include <linux/string.h>

20 #include <bcmdefs.h>

21 #include <linux/module.h>

22 #include <linux/pci.h>

23 #include <bcmutils.h>

24 #include <siutils.h>

25 #include <bcmdevs.h>

26 #include <hndsoc.h>

27 #include <sbchipc.h>

28 #include <pci_core.h>

29 #include <pcie_core.h>

30 #include <nicpci.h>

31 #include <bcmnvram.h>

32 #include <bcmsrom.h>

33 #include <pcicfg.h>

34 #include <sbsocram.h>

35 #ifdef BCMSDIO

36 #include <bcmsdh.h>

37 #include <sdio.h>

38 #include <sbsdio.h>

39 #include <sbhnddma.h>

40 #include <sbsdpcmdev.h>

41 #include <bcmsdpcm.h>

42 #endif /* BCMSDIO */

43 #include <wlc_pmu.h>

45 /* this file now contains only definitions for sb functions, only necessary

46 *for devices using Sonics backplanes (bcm4329)

47 */

49 /* if an amba SDIO device is supported, please further restrict the inclusion

50 * of this file

51 */

52 #ifdef BCMSDIO

53 #include "siutils_priv.h"

54 #endif

56 /* local prototypes */

57 static si_info_t *si_doattach(si_info_t *sii, uint devid, void *regs,

58 uint bustype, void *sdh, char **vars,

59 uint *varsz);

60 static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,

61 void *sdh);

62 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,

63 u32 savewin, uint *origidx, void *regs);

64 static void si_nvram_process(si_info_t *sii, char *pvars);

66 /* dev path concatenation util */

67 static char *si_devpathvar(si_t *sih, char *var, int len, const char *name);

68 static bool _si_clkctl_cc(si_info_t *sii, uint mode);

69 static bool si_ispcie(si_info_t *sii);

70 static uint socram_banksize(si_info_t *sii, sbsocramregs_t *r,

71 u8 idx, u8 mtype);

73 /* global variable to indicate reservation/release of gpio's */

74 static u32 si_gpioreservation;

76 /*

77 * Allocate a si handle.

78 * devid - pci device id (used to determine chip#)

79 * osh - opaque OS handle

80 * regs - virtual address of initial core registers

81 * bustype - pci/sb/sdio/etc

82 * vars - pointer to a pointer area for "environment" variables

83 * varsz - pointer to int to return the size of the vars

84 */

85 si_t *si_attach(uint devid, void *regs, uint bustype,

86 void *sdh, char **vars, uint *varsz)

87 {

88 si_info_t *sii;

90 /* alloc si_info_t */

91 sii = kmalloc(sizeof(si_info_t), GFP_ATOMIC);

92 if (sii == NULL) {

93 SI_ERROR(("si_attach: malloc failed!\n"));

94 return NULL;

95 }

97 if (si_doattach(sii, devid, regs, bustype, sdh, vars, varsz) ==

98 NULL) {

99 kfree(sii);

100 return NULL;

101 }

102 sii->vars = vars ? *vars : NULL;

103 sii->varsz = varsz ? *varsz : 0;

104

105 return (si_t *) sii;

106 }

107

108 /* global kernel resource */

109 static si_info_t ksii;

110

111 static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,

112 void *sdh)

113 {

114

115 #ifndef BRCM_FULLMAC

116 /* kludge to enable the clock on the 4306 which lacks a slowclock */

117 if (bustype == PCI_BUS && !si_ispcie(sii))

118 si_clkctl_xtal(&sii->pub, XTAL | PLL, ON);

119 #endif

120

121 #if defined(BCMSDIO)

122 if (bustype == SDIO_BUS) {

123 int err;

124 u8 clkset;

125

126 /* Try forcing SDIO core to do ALPAvail request only */

127 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;

128 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,

129 clkset, &err);

130 if (!err) {

131 u8 clkval;

132

133 /* If register supported, wait for ALPAvail and then force ALP */

134 clkval =

135 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,

136 SBSDIO_FUNC1_CHIPCLKCSR, NULL);

137 if ((clkval & ~SBSDIO_AVBITS) == clkset) {

138 SPINWAIT(((clkval =

139 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,

140 SBSDIO_FUNC1_CHIPCLKCSR,

141 NULL)),

142 !SBSDIO_ALPAV(clkval)),

143 PMU_MAX_TRANSITION_DLY);

144 if (!SBSDIO_ALPAV(clkval)) {

145 SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n", clkval));

146 return false;

147 }

148 clkset =

149 SBSDIO_FORCE_HW_CLKREQ_OFF |

150 SBSDIO_FORCE_ALP;

151 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,

152 SBSDIO_FUNC1_CHIPCLKCSR,

153 clkset, &err);

154 udelay(65);

155 }

156 }

157

158 /* Also, disable the extra SDIO pull-ups */

159 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,

160 NULL);

161 }

162 #endif /* defined(BCMSDIO) */

163

164 return true;

165 }

166

167 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,

168 u32 savewin, uint *origidx, void *regs)

169 {

170 bool pci, pcie;

171 uint i;

172 uint pciidx, pcieidx, pcirev, pcierev;

173

174 cc = si_setcoreidx(&sii->pub, SI_CC_IDX);

175

176 /* get chipcommon rev */

177 sii->pub.ccrev = (int)si_corerev(&sii->pub);

178

179 /* get chipcommon chipstatus */

180 if (sii->pub.ccrev >= 11)

181 sii->pub.chipst = R_REG(&cc->chipstatus);

182

183 /* get chipcommon capabilites */

184 sii->pub.cccaps = R_REG(&cc->capabilities);

185 /* get chipcommon extended capabilities */

186

187 #ifndef BRCM_FULLMAC

188 if (sii->pub.ccrev >= 35)

189 sii->pub.cccaps_ext = R_REG(&cc->capabilities_ext);

190 #endif

191 /* get pmu rev and caps */

192 if (sii->pub.cccaps & CC_CAP_PMU) {

193 sii->pub.pmucaps = R_REG(&cc->pmucapabilities);

194 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;

195 }

196

197 /*

198 SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n",

199 sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,

200 sii->pub.pmucaps));

201 */

202

203 /* figure out bus/orignal core idx */

204 sii->pub.buscoretype = NODEV_CORE_ID;

205 sii->pub.buscorerev = NOREV;

206 sii->pub.buscoreidx = BADIDX;

207

208 pci = pcie = false;

209 pcirev = pcierev = NOREV;

210 pciidx = pcieidx = BADIDX;

211

212 for (i = 0; i < sii->numcores; i++) {

213 uint cid, crev;

214

215 si_setcoreidx(&sii->pub, i);

216 cid = si_coreid(&sii->pub);

217 crev = si_corerev(&sii->pub);

218

219 /* Display cores found */

220 SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",

221 i, cid, crev, sii->coresba[i], sii->regs[i]));

222

223 if (bustype == PCI_BUS) {

224 if (cid == PCI_CORE_ID) {

225 pciidx = i;

226 pcirev = crev;

227 pci = true;

228 } else if (cid == PCIE_CORE_ID) {

229 pcieidx = i;

230 pcierev = crev;

231 pcie = true;

232 }

233 }

234 #ifdef BCMSDIO

235 else if (((bustype == SDIO_BUS) ||

236 (bustype == SPI_BUS)) &&

237 ((cid == PCMCIA_CORE_ID) || (cid == SDIOD_CORE_ID))) {

238 sii->pub.buscorerev = crev;

239 sii->pub.buscoretype = cid;

240 sii->pub.buscoreidx = i;

241 }

242 #endif /* BCMSDIO */

243

244 /* find the core idx before entering this func. */

245 if ((savewin && (savewin == sii->coresba[i])) ||

246 (regs == sii->regs[i]))

247 *origidx = i;

248 }

249

250 #ifdef BRCM_FULLMAC

251 SI_MSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx,

252 sii->pub.buscoretype, sii->pub.buscorerev));

253

254 /* Make sure any on-chip ARM is off (in case strapping is wrong),

255 * or downloaded code was

256 * already running.

257 */

258 if ((bustype == SDIO_BUS) || (bustype == SPI_BUS)) {

259 if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) ||

260 si_setcore(&sii->pub, ARMCM3_CORE_ID, 0))

261 si_core_disable(&sii->pub, 0);

262 }

263 #else

264 if (pci && pcie) {

265 if (si_ispcie(sii))

266 pci = false;

267 else

268 pcie = false;

269 }

270 if (pci) {

271 sii->pub.buscoretype = PCI_CORE_ID;

272 sii->pub.buscorerev = pcirev;

273 sii->pub.buscoreidx = pciidx;

274 } else if (pcie) {

275 sii->pub.buscoretype = PCIE_CORE_ID;

276 sii->pub.buscorerev = pcierev;

277 sii->pub.buscoreidx = pcieidx;

278 }

279

280 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx,

281 sii->pub.buscoretype, sii->pub.buscorerev));

282

283 /* fixup necessary chip/core configurations */

284 if (sii->pub.bustype == PCI_BUS) {

285 if (SI_FAST(sii)) {

286 if (!sii->pch) {

287 sii->pch = (void *)pcicore_init(

288 &sii->pub, sii->pbus,

289 (void *)PCIEREGS(sii));

290 if (sii->pch == NULL)

291 return false;

292 }

293 }

294 if (si_pci_fixcfg(&sii->pub)) {

295 SI_ERROR(("si_doattach: sb_pci_fixcfg failed\n"));

296 return false;

297 }

298 }

299 #endif

300 /* return to the original core */

301 si_setcoreidx(&sii->pub, *origidx);

302

303 return true;

304 }

305

306 static __used void si_nvram_process(si_info_t *sii, char *pvars)

307 {

308 uint w = 0;

309

310 /* get boardtype and boardrev */

311 switch (sii->pub.bustype) {

312 case PCI_BUS:

313 /* do a pci config read to get subsystem id and subvendor id */

314 pci_read_config_dword(sii->pbus, PCI_SUBSYSTEM_VENDOR_ID,

315 &w);

316 /* Let nvram variables override subsystem Vend/ID */

317 sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub,

318 "boardvendor");

319 if (sii->pub.boardvendor == 0)

320 sii->pub.boardvendor = w & 0xffff;

321 else

322 SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", sii->pub.boardvendor, w & 0xffff));

323 sii->pub.boardtype = (u16)si_getdevpathintvar(&sii->pub,

324 "boardtype");

325 if (sii->pub.boardtype == 0)

326 sii->pub.boardtype = (w >> 16) & 0xffff;

327 else

328 SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n", sii->pub.boardtype, (w >> 16) & 0xffff));

329 break;

330

331 #ifdef BCMSDIO

332 case SDIO_BUS:

333 #endif

334 sii->pub.boardvendor = getintvar(pvars, "manfid");

335 sii->pub.boardtype = getintvar(pvars, "prodid");

336 break;

337

338 #ifdef BCMSDIO

339 case SPI_BUS:

340 sii->pub.boardvendor = PCI_VENDOR_ID_BROADCOM;

341 sii->pub.boardtype = SPI_BOARD;

342 break;

343 #endif

344

345 case SI_BUS:

346 case JTAG_BUS:

347 sii->pub.boardvendor = PCI_VENDOR_ID_BROADCOM;

348 sii->pub.boardtype = getintvar(pvars, "prodid");

349 if (pvars == NULL || (sii->pub.boardtype == 0)) {

350 sii->pub.boardtype = getintvar(NULL, "boardtype");

351 if (sii->pub.boardtype == 0)

352 sii->pub.boardtype = 0xffff;

353 }

354 break;

355 }

356

357 if (sii->pub.boardtype == 0) {

358 SI_ERROR(("si_doattach: unknown board type\n"));

359 }

360

361 sii->pub.boardflags = getintvar(pvars, "boardflags");

362 }

363

364 /* this is will make Sonics calls directly, since Sonics is no longer supported in the Si abstraction */

365 /* this has been customized for the bcm 4329 ONLY */

366 #ifdef BRCM_FULLMAC

367 static si_info_t *si_doattach(si_info_t *sii, uint devid,

368 void *regs, uint bustype, void *pbus,

369 char **vars, uint *varsz)

370 {

371 struct si_pub *sih = &sii->pub;

372 u32 w, savewin;

373 chipcregs_t *cc;

374 uint origidx;

375

376 memset((unsigned char *) sii, 0, sizeof(si_info_t));

377

378 savewin = 0;

379

380 sih->buscoreidx = BADIDX;

381

382 sii->curmap = regs;

383 sii->pbus = pbus;

384

385 /* find Chipcommon address */

386 cc = (chipcregs_t *) sii->curmap;

387 sih->bustype = bustype;

388

389 /* bus/core/clk setup for register access */

390 if (!si_buscore_prep(sii, bustype, devid, pbus)) {

391 SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",

392 bustype));

393 return NULL;

394 }

395

396 /* ChipID recognition.

397 * We assume we can read chipid at offset 0 from the regs arg.

398 * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),

399 * some way of recognizing them needs to be added here.

400 */

401 w = R_REG(&cc->chipid);

402 sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;

403 /* Might as wll fill in chip id rev & pkg */

404 sih->chip = w & CID_ID_MASK;

405 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;

406 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;

407

408 if ((sih->chip == BCM4329_CHIP_ID) &&

409 (sih->chippkg != BCM4329_289PIN_PKG_ID))

410 sih->chippkg = BCM4329_182PIN_PKG_ID;

411

412 sih->issim = IS_SIM(sih->chippkg);

413

414 /* scan for cores */

415 /* SI_MSG(("Found chip type SB (0x%08x)\n", w)); */

416 sb_scan(&sii->pub, regs, devid);

417

418 /* no cores found, bail out */

419 if (sii->numcores == 0) {

420 SI_ERROR(("si_doattach: could not find any cores\n"));

421 return NULL;

422 }

423 /* bus/core/clk setup */

424 origidx = SI_CC_IDX;

425 if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {

426 SI_ERROR(("si_doattach: si_buscore_setup failed\n"));

427 goto exit;

428 }

429

430 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);

431 W_REG(&cc->gpiopullup, 0);

432 W_REG(&cc->gpiopulldown, 0);

433 sb_setcoreidx(sih, origidx);

434

435 return sii;

436

437 exit:

438 return NULL;

439 }

440 #else /* BRCM_FULLMAC */

441 static si_info_t *si_doattach(si_info_t *sii, uint devid,

442 void *regs, uint bustype, void *pbus,

443 char **vars, uint *varsz)

444 {

445 struct si_pub *sih = &sii->pub;

446 u32 w, savewin;

447 chipcregs_t *cc;

448 char *pvars = NULL;

449 uint origidx;

450

451 memset((unsigned char *) sii, 0, sizeof(si_info_t));

452

453 savewin = 0;

454

455 sih->buscoreidx = BADIDX;

456

457 sii->curmap = regs;

458 sii->pbus = pbus;

459

460 /* check to see if we are a si core mimic'ing a pci core */

461 if (bustype == PCI_BUS) {

462 pci_read_config_dword(sii->pbus, PCI_SPROM_CONTROL, &w);

463 if (w == 0xffffffff) {

464 SI_ERROR(("%s: incoming bus is PCI but it's a lie, "

465 " switching to SI devid:0x%x\n",

466 __func__, devid));

467 bustype = SI_BUS;

468 }

469 }

470

471 /* find Chipcommon address */

472 if (bustype == PCI_BUS) {

473 pci_read_config_dword(sii->pbus, PCI_BAR0_WIN, &savewin);

474 if (!GOODCOREADDR(savewin, SI_ENUM_BASE))

475 savewin = SI_ENUM_BASE;

476 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN,

477 SI_ENUM_BASE);

478 cc = (chipcregs_t *) regs;

479 } else {

480 cc = (chipcregs_t *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);

481 }

482

483 sih->bustype = bustype;

484

485 /* bus/core/clk setup for register access */

486 if (!si_buscore_prep(sii, bustype, devid, pbus)) {

487 SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",

488 bustype));

489 return NULL;

490 }

491

492 /* ChipID recognition.

493 * We assume we can read chipid at offset 0 from the regs arg.

494 * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),

495 * some way of recognizing them needs to be added here.

496 */

497 w = R_REG(&cc->chipid);

498 sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;

499 /* Might as wll fill in chip id rev & pkg */

500 sih->chip = w & CID_ID_MASK;

501 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;

502 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;

503

504 sih->issim = IS_SIM(sih->chippkg);

505

506 /* scan for cores */

507 if (sii->pub.socitype == SOCI_AI) {

508 SI_MSG(("Found chip type AI (0x%08x)\n", w));

509 /* pass chipc address instead of original core base */

510 ai_scan(&sii->pub, (void *)cc, devid);

511 } else {

512 SI_ERROR(("Found chip of unknown type (0x%08x)\n", w));

513 return NULL;

514 }

515 /* no cores found, bail out */

516 if (sii->numcores == 0) {

517 SI_ERROR(("si_doattach: could not find any cores\n"));

518 return NULL;

519 }

520 /* bus/core/clk setup */

521 origidx = SI_CC_IDX;

522 if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {

523 SI_ERROR(("si_doattach: si_buscore_setup failed\n"));

524 goto exit;

525 }

526

527 /* assume current core is CC */

528 if ((sii->pub.ccrev == 0x25)

529 &&

530 ((sih->chip == BCM43236_CHIP_ID

531 || sih->chip == BCM43235_CHIP_ID

532 || sih->chip == BCM43238_CHIP_ID)

533 && (sii->pub.chiprev <= 2))) {

534

535 if ((cc->chipstatus & CST43236_BP_CLK) != 0) {

536 uint clkdiv;

537 clkdiv = R_REG(&cc->clkdiv);

538 /* otp_clk_div is even number, 120/14 < 9mhz */

539 clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT);

540 W_REG(&cc->clkdiv, clkdiv);

541 SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv));

542 }

543 udelay(10);

544 }

545

546 /* Init nvram from flash if it exists */

547 nvram_init((void *)&(sii->pub));

548

549 /* Init nvram from sprom/otp if they exist */

550 if (srom_var_init

551 (&sii->pub, bustype, regs, vars, varsz)) {

552 SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));

553 goto exit;

554 }

555 pvars = vars ? *vars : NULL;

556 si_nvram_process(sii, pvars);

557

558 /* === NVRAM, clock is ready === */

559 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);

560 W_REG(&cc->gpiopullup, 0);

561 W_REG(&cc->gpiopulldown, 0);

562 si_setcoreidx(sih, origidx);

563

564 /* PMU specific initializations */

565 if (PMUCTL_ENAB(sih)) {

566 u32 xtalfreq;

567 si_pmu_init(sih);

568 si_pmu_chip_init(sih);

569 xtalfreq = getintvar(pvars, "xtalfreq");

570 /* If xtalfreq var not available, try to measure it */

571 if (xtalfreq == 0)

572 xtalfreq = si_pmu_measure_alpclk(sih);

573 si_pmu_pll_init(sih, xtalfreq);

574 si_pmu_res_init(sih);

575 si_pmu_swreg_init(sih);

576 }

577

578 /* setup the GPIO based LED powersave register */

579 w = getintvar(pvars, "leddc");

580 if (w == 0)

581 w = DEFAULT_GPIOTIMERVAL;

582 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);

583

584 if (PCIE(sii)) {

585 pcicore_attach(sii->pch, pvars, SI_DOATTACH);

586 }

587

588 if ((sih->chip == BCM43224_CHIP_ID) ||

589 (sih->chip == BCM43421_CHIP_ID)) {

590 /* enable 12 mA drive strenth for 43224 and set chipControl register bit 15 */

591 if (sih->chiprev == 0) {

592 SI_MSG(("Applying 43224A0 WARs\n"));

593 si_corereg(sih, SI_CC_IDX,

594 offsetof(chipcregs_t, chipcontrol),

595 CCTRL43224_GPIO_TOGGLE,

596 CCTRL43224_GPIO_TOGGLE);

597 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,

598 CCTRL_43224A0_12MA_LED_DRIVE);

599 }

600 if (sih->chiprev >= 1) {

601 SI_MSG(("Applying 43224B0+ WARs\n"));

602 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,

603 CCTRL_43224B0_12MA_LED_DRIVE);

604 }

605 }

606

607 if (sih->chip == BCM4313_CHIP_ID) {

608 /* enable 12 mA drive strenth for 4313 and set chipControl register bit 1 */

609 SI_MSG(("Applying 4313 WARs\n"));

610 si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,

611 CCTRL_4313_12MA_LED_DRIVE);

612 }

613

614 if (sih->chip == BCM4331_CHIP_ID) {

615 /* Enable Ext PA lines depending on chip package option */

616 si_chipcontrl_epa4331(sih, true);

617 }

618

619 return sii;

620 exit:

621 if (sih->bustype == PCI_BUS) {

622 if (sii->pch)

623 pcicore_deinit(sii->pch);

624 sii->pch = NULL;

625 }

626

627 return NULL;

628 }

629 #endif /* BRCM_FULLMAC */

630

631 /* may be called with core in reset */

632 void si_detach(si_t *sih)

633 {

634 si_info_t *sii;

635 uint idx;

636

637 struct si_pub *si_local = NULL;

638 memcpy(&si_local, &sih, sizeof(si_t **));

639

640 sii = SI_INFO(sih);

641

642 if (sii == NULL)

643 return;

644

645 if (sih->bustype == SI_BUS)

646 for (idx = 0; idx < SI_MAXCORES; idx++)

647 if (sii->regs[idx]) {

648 iounmap(sii->regs[idx]);

649 sii->regs[idx] = NULL;

650 }

651

652 #ifndef BRCM_FULLMAC

653 nvram_exit((void *)si_local); /* free up nvram buffers */

654

655 if (sih->bustype == PCI_BUS) {

656 if (sii->pch)

657 pcicore_deinit(sii->pch);

658 sii->pch = NULL;

659 }

660 #endif

661 #if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS)

662 if (sii != &ksii)

663 #endif /* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */

664 kfree(sii);

665 }

666

667 /* register driver interrupt disabling and restoring callback functions */

668 void

669 si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,

670 void *intrsenabled_fn, void *intr_arg)

671 {

672 si_info_t *sii;

673

674 sii = SI_INFO(sih);

675 sii->intr_arg = intr_arg;

676 sii->intrsoff_fn = (si_intrsoff_t) intrsoff_fn;

677 sii->intrsrestore_fn = (si_intrsrestore_t) intrsrestore_fn;

678 sii->intrsenabled_fn = (si_intrsenabled_t) intrsenabled_fn;

679 /* save current core id. when this function called, the current core

680 * must be the core which provides driver functions(il, et, wl, etc.)

681 */

682 sii->dev_coreid = sii->coreid[sii->curidx];

683 }

684

685 void si_deregister_intr_callback(si_t *sih)

686 {

687 si_info_t *sii;

688

689 sii = SI_INFO(sih);

690 sii->intrsoff_fn = NULL;

691 }

692

693 uint si_flag(si_t *sih)

694 {

695 if (sih->socitype == SOCI_AI)

696 return ai_flag(sih);

697 else {

698 return 0;

699 }

700 }

701

702 void si_setint(si_t *sih, int siflag)

703 {

704 if (sih->socitype == SOCI_AI)

705 ai_setint(sih, siflag);

706 }

707

708 #ifndef BCMSDIO

709 uint si_coreid(si_t *sih)

710 {

711 si_info_t *sii;

712

713 sii = SI_INFO(sih);

714 return sii->coreid[sii->curidx];

715 }

716 #endif

717

718 uint si_coreidx(si_t *sih)

719 {

720 si_info_t *sii;

721

722 sii = SI_INFO(sih);

723 return sii->curidx;

724 }

725

726 bool si_backplane64(si_t *sih)

727 {

728 return (sih->cccaps & CC_CAP_BKPLN64) != 0;

729 }

730

731 #ifndef BCMSDIO

732 uint si_corerev(si_t *sih)

733 {

734 if (sih->socitype == SOCI_AI)

735 return ai_corerev(sih);

736 return 0;

737 }

738 #endif

739

740 /* return index of coreid or BADIDX if not found */

741 uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit)

742 {

743 si_info_t *sii;

744 uint found;

745 uint i;

746

747 sii = SI_INFO(sih);

748

749 found = 0;

750

751 for (i = 0; i < sii->numcores; i++)

752 if (sii->coreid[i] == coreid) {

753 if (found == coreunit)

754 return i;

755 found++;

756 }

757

758 return BADIDX;

759 }

760

761 /*

762 * This function changes logical "focus" to the indicated core;

763 * must be called with interrupts off.

764 * Moreover, callers should keep interrupts off during switching out of and back to d11 core

765 */

766 void *si_setcore(si_t *sih, uint coreid, uint coreunit)

767 {

768 uint idx;

769

770 idx = si_findcoreidx(sih, coreid, coreunit);

771 if (!GOODIDX(idx))

772 return NULL;

773

774 if (sih->socitype == SOCI_AI)

775 return ai_setcoreidx(sih, idx);

776 else {

777 #ifdef BCMSDIO

778 return sb_setcoreidx(sih, idx);

779 #else

780 return NULL;

781 #endif

782 }

783 }

784

785 #ifndef BCMSDIO

786 void *si_setcoreidx(si_t *sih, uint coreidx)

787 {

788 if (sih->socitype == SOCI_AI)

789 return ai_setcoreidx(sih, coreidx);

790 else {

791 return NULL;

792 }

793 }

794 #endif

795

796 /* Turn off interrupt as required by sb_setcore, before switch core */

797 void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)

798 {

799 void *cc;

800 si_info_t *sii;

801

802 sii = SI_INFO(sih);

803

804 if (SI_FAST(sii)) {

805 /* Overloading the origidx variable to remember the coreid,

806 * this works because the core ids cannot be confused with

807 * core indices.

808 */

809 *origidx = coreid;

810 if (coreid == CC_CORE_ID)

811 return (void *)CCREGS_FAST(sii);

812 else if (coreid == sih->buscoretype)

813 return (void *)PCIEREGS(sii);

814 }

815 INTR_OFF(sii, *intr_val);

816 *origidx = sii->curidx;

817 cc = si_setcore(sih, coreid, 0);

818

819 return cc;

820 }

821

822 /* restore coreidx and restore interrupt */

823 void si_restore_core(si_t *sih, uint coreid, uint intr_val)

824 {

825 si_info_t *sii;

826

827 sii = SI_INFO(sih);

828 if (SI_FAST(sii)

829 && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))

830 return;

831

832 si_setcoreidx(sih, coreid);

833 INTR_RESTORE(sii, intr_val);

834 }

835

836 u32 si_core_cflags(si_t *sih, u32 mask, u32 val)

837 {

838 if (sih->socitype == SOCI_AI)

839 return ai_core_cflags(sih, mask, val);

840 else {

841 return 0;

842 }

843 }

844

845 u32 si_core_sflags(si_t *sih, u32 mask, u32 val)

846 {

847 if (sih->socitype == SOCI_AI)

848 return ai_core_sflags(sih, mask, val);

849 else {

850 return 0;

851 }

852 }

853

854 bool si_iscoreup(si_t *sih)

855 {

856 if (sih->socitype == SOCI_AI)

857 return ai_iscoreup(sih);

858 else {

859 #ifdef BCMSDIO

860 return sb_iscoreup(sih);

861 #else

862 return false;

863 #endif

864 }

865 }

866

867 void si_write_wrapperreg(si_t *sih, u32 offset, u32 val)

868 {

869 /* only for 4319, no requirement for SOCI_SB */

870 if (sih->socitype == SOCI_AI) {

871 ai_write_wrap_reg(sih, offset, val);

872 }

873 }

874

875 uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)

876 {

877

878 if (sih->socitype == SOCI_AI)

879 return ai_corereg(sih, coreidx, regoff, mask, val);

880 else {

881 #ifdef BCMSDIO

882 return sb_corereg(sih, coreidx, regoff, mask, val);

883 #else

884 return 0;

885 #endif

886 }

887 }

888

889 void si_core_disable(si_t *sih, u32 bits)

890 {

891

892 if (sih->socitype == SOCI_AI)

893 ai_core_disable(sih, bits);

894 #ifdef BCMSDIO

895 else

896 sb_core_disable(sih, bits);

897 #endif

898 }

899

900 void si_core_reset(si_t *sih, u32 bits, u32 resetbits)

901 {

902 if (sih->socitype == SOCI_AI)

903 ai_core_reset(sih, bits, resetbits);

904 #ifdef BCMSDIO

905 else

906 sb_core_reset(sih, bits, resetbits);

907 #endif

908 }

909

910 u32 si_alp_clock(si_t *sih)

911 {

912 if (PMUCTL_ENAB(sih))

913 return si_pmu_alp_clock(sih);

914

915 return ALP_CLOCK;

916 }

917

918 u32 si_ilp_clock(si_t *sih)

919 {

920 if (PMUCTL_ENAB(sih))

921 return si_pmu_ilp_clock(sih);

922

923 return ILP_CLOCK;

924 }

925

926 /* set chip watchdog reset timer to fire in 'ticks' */

927 #ifdef BRCM_FULLMAC

928 void

929 si_watchdog(si_t *sih, uint ticks)

930 {

931 if (PMUCTL_ENAB(sih)) {

932

933 if ((sih->chip == BCM4319_CHIP_ID) && (sih->chiprev == 0) &&

934 (ticks != 0)) {

935 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t,

936 clk_ctl_st), ~0, 0x2);

937 si_setcore(sih, USB20D_CORE_ID, 0);

938 si_core_disable(sih, 1);

939 si_setcore(sih, CC_CORE_ID, 0);

940 }

941

942 if (ticks == 1)

943 ticks = 2;

944 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog),

945 ~0, ticks);

946 } else {

947 /* instant NMI */

948 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog),

949 ~0, ticks);

950 }

951 }

952 #else

953 void si_watchdog(si_t *sih, uint ticks)

954 {

955 uint nb, maxt;

956

957 if (PMUCTL_ENAB(sih)) {

958

959 if ((sih->chip == BCM4319_CHIP_ID) &&

960 (sih->chiprev == 0) && (ticks != 0)) {

961 si_corereg(sih, SI_CC_IDX,

962 offsetof(chipcregs_t, clk_ctl_st), ~0, 0x2);

963 si_setcore(sih, USB20D_CORE_ID, 0);

964 si_core_disable(sih, 1);

965 si_setcore(sih, CC_CORE_ID, 0);

966 }

967

968 nb = (sih->ccrev < 26) ? 16 : ((sih->ccrev >= 37) ? 32 : 24);

969 /* The mips compiler uses the sllv instruction,

970 * so we specially handle the 32-bit case.

971 */

972 if (nb == 32)

973 maxt = 0xffffffff;

974 else

975 maxt = ((1 << nb) - 1);

976

977 if (ticks == 1)

978 ticks = 2;

979 else if (ticks > maxt)

980 ticks = maxt;

981

982 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog),

983 ~0, ticks);

984 } else {

985 /* make sure we come up in fast clock mode; or if clearing, clear clock */

986 si_clkctl_cc(sih, ticks ? CLK_FAST : CLK_DYNAMIC);

987 maxt = (1 << 28) - 1;

988 if (ticks > maxt)

989 ticks = maxt;

990

991 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog), ~0,

992 ticks);

993 }

994 }

995 #endif

996

997 /* return the slow clock source - LPO, XTAL, or PCI */

998 static uint si_slowclk_src(si_info_t *sii)

999 {

1000 chipcregs_t *cc;

1001 u32 val;

1002

1003 if (sii->pub.ccrev < 6) {

1004 if (sii->pub.bustype == PCI_BUS) {

1005 pci_read_config_dword(sii->pbus, PCI_GPIO_OUT,

1006 &val);

1007 if (val & PCI_CFG_GPIO_SCS)

1008 return SCC_SS_PCI;

1009 }

1010 return SCC_SS_XTAL;

1011 } else if (sii->pub.ccrev < 10) {

1012 cc = (chipcregs_t *) si_setcoreidx(&sii->pub, sii->curidx);

1013 return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;

1014 } else /* Insta-clock */

1015 return SCC_SS_XTAL;

1016 }

1017

1018 /* return the ILP (slowclock) min or max frequency */

1019 static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)

1020 {

1021 u32 slowclk;

1022 uint div;

1023

1024 slowclk = si_slowclk_src(sii);

1025 if (sii->pub.ccrev < 6) {

1026 if (slowclk == SCC_SS_PCI)

1027 return max_freq ? (PCIMAXFREQ / 64)

1028 : (PCIMINFREQ / 64);

1029 else

1030 return max_freq ? (XTALMAXFREQ / 32)

1031 : (XTALMINFREQ / 32);

1032 } else if (sii->pub.ccrev < 10) {

1033 div = 4 *

1034 (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >>

1035 SCC_CD_SHIFT) + 1);

1036 if (slowclk == SCC_SS_LPO)

1037 return max_freq ? LPOMAXFREQ : LPOMINFREQ;

1038 else if (slowclk == SCC_SS_XTAL)

1039 return max_freq ? (XTALMAXFREQ / div)

1040 : (XTALMINFREQ / div);

1041 else if (slowclk == SCC_SS_PCI)

1042 return max_freq ? (PCIMAXFREQ / div)

1043 : (PCIMINFREQ / div);

1044 } else {

1045 /* Chipc rev 10 is InstaClock */

1046 div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;

1047 div = 4 * (div + 1);

1048 return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);

1049 }

1050 return 0;

1051 }

1052

1053 static void si_clkctl_setdelay(si_info_t *sii, void *chipcregs)

1054 {

1055 chipcregs_t *cc = (chipcregs_t *) chipcregs;

1056 uint slowmaxfreq, pll_delay, slowclk;

1057 uint pll_on_delay, fref_sel_delay;

1058

1059 pll_delay = PLL_DELAY;

1060

1061 /* If the slow clock is not sourced by the xtal then add the xtal_on_delay

1062 * since the xtal will also be powered down by dynamic clk control logic.

1063 */

1064

1065 slowclk = si_slowclk_src(sii);

1066 if (slowclk != SCC_SS_XTAL)

1067 pll_delay += XTAL_ON_DELAY;

1068

1069 /* Starting with 4318 it is ILP that is used for the delays */

1070 slowmaxfreq =

1071 si_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc);

1072

1073 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;

1074 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;

1075

1076 W_REG(&cc->pll_on_delay, pll_on_delay);

1077 W_REG(&cc->fref_sel_delay, fref_sel_delay);

1078 }

1079

1080 /* initialize power control delay registers */

1081 void si_clkctl_init(si_t *sih)

1082 {

1083 si_info_t *sii;

1084 uint origidx = 0;

1085 chipcregs_t *cc;

1086 bool fast;

1087

1088 if (!CCCTL_ENAB(sih))

1089 return;

1090

1091 sii = SI_INFO(sih);

1092 fast = SI_FAST(sii);

1093 if (!fast) {

1094 origidx = sii->curidx;

1095 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);

1096 if (cc == NULL)

1097 return;

1098 } else {

1099 cc = (chipcregs_t *) CCREGS_FAST(sii);

1100 if (cc == NULL)

1101 return;

1102 }

1103

1104 /* set all Instaclk chip ILP to 1 MHz */

1105 if (sih->ccrev >= 10)

1106 SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK,

1107 (ILP_DIV_1MHZ << SYCC_CD_SHIFT));

1108

1109 si_clkctl_setdelay(sii, (void *)cc);

1110

1111 if (!fast)

1112 si_setcoreidx(sih, origidx);

1113 }

1114

1115 /* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */

1116 u16 si_clkctl_fast_pwrup_delay(si_t *sih)

1117 {

1118 si_info_t *sii;

1119 uint origidx = 0;

1120 chipcregs_t *cc;

1121 uint slowminfreq;

1122 u16 fpdelay;

1123 uint intr_val = 0;

1124 bool fast;

1125

1126 sii = SI_INFO(sih);

1127 if (PMUCTL_ENAB(sih)) {

1128 INTR_OFF(sii, intr_val);

1129 fpdelay = si_pmu_fast_pwrup_delay(sih);

1130 INTR_RESTORE(sii, intr_val);

1131 return fpdelay;

1132 }

1133

1134 if (!CCCTL_ENAB(sih))

1135 return 0;

1136

1137 fast = SI_FAST(sii);

1138 fpdelay = 0;

1139 if (!fast) {

1140 origidx = sii->curidx;

1141 INTR_OFF(sii, intr_val);

1142 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);

1143 if (cc == NULL)

1144 goto done;

1145 } else {

1146 cc = (chipcregs_t *) CCREGS_FAST(sii);

1147 if (cc == NULL)

1148 goto done;

1149 }

1150

1151 slowminfreq = si_slowclk_freq(sii, false, cc);

1152 fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) +

1153 (slowminfreq - 1)) / slowminfreq;

1154

1155 done:

1156 if (!fast) {

1157 si_setcoreidx(sih, origidx);

1158 INTR_RESTORE(sii, intr_val);

1159 }

1160 return fpdelay;

1161 }

1162

1163 /* turn primary xtal and/or pll off/on */

1164 int si_clkctl_xtal(si_t *sih, uint what, bool on)

1165 {

1166 si_info_t *sii;

1167 u32 in, out, outen;

1168

1169 sii = SI_INFO(sih);

1170

1171 switch (sih->bustype) {

1172

1173 #ifdef BCMSDIO

1174 case SDIO_BUS:

1175 return -1;

1176 #endif /* BCMSDIO */

1177

1178 case PCI_BUS:

1179 /* pcie core doesn't have any mapping to control the xtal pu */

1180 if (PCIE(sii))

1181 return -1;

1182

1183 pci_read_config_dword(sii->pbus, PCI_GPIO_IN, &in);

1184 pci_read_config_dword(sii->pbus, PCI_GPIO_OUT, &out);

1185 pci_read_config_dword(sii->pbus, PCI_GPIO_OUTEN, &outen);

1186

1187 /*

1188 * Avoid glitching the clock if GPRS is already using it.

1189 * We can't actually read the state of the PLLPD so we infer it

1190 * by the value of XTAL_PU which *is* readable via gpioin.

1191 */

1192 if (on && (in & PCI_CFG_GPIO_XTAL))

1193 return 0;

1194

1195 if (what & XTAL)

1196 outen |= PCI_CFG_GPIO_XTAL;

1197 if (what & PLL)

1198 outen |= PCI_CFG_GPIO_PLL;

1199

1200 if (on) {

1201 /* turn primary xtal on */

1202 if (what & XTAL) {

1203 out |= PCI_CFG_GPIO_XTAL;

1204 if (what & PLL)

1205 out |= PCI_CFG_GPIO_PLL;

1206 pci_write_config_dword(sii->pbus,

1207 PCI_GPIO_OUT, out);

1208 pci_write_config_dword(sii->pbus,

1209 PCI_GPIO_OUTEN, outen);

1210 udelay(XTAL_ON_DELAY);

1211 }

1212

1213 /* turn pll on */

1214 if (what & PLL) {

1215 out &= ~PCI_CFG_GPIO_PLL;

1216 pci_write_config_dword(sii->pbus,

1217 PCI_GPIO_OUT, out);

1218 mdelay(2);

1219 }

1220 } else {

1221 if (what & XTAL)

1222 out &= ~PCI_CFG_GPIO_XTAL;

1223 if (what & PLL)

1224 out |= PCI_CFG_GPIO_PLL;

1225 pci_write_config_dword(sii->pbus,

1226 PCI_GPIO_OUT, out);

1227 pci_write_config_dword(sii->pbus,

1228 PCI_GPIO_OUTEN, outen);

1229 }

1230

1231 default:

1232 return -1;

1233 }

1234

1235 return 0;

1236 }

1237

1238 /*

1239 * clock control policy function through chipcommon

1240 *

1241 * set dynamic clk control mode (forceslow, forcefast, dynamic)

1242 * returns true if we are forcing fast clock

1243 * this is a wrapper over the next internal function

1244 * to allow flexible policy settings for outside caller

1245 */

1246 bool si_clkctl_cc(si_t *sih, uint mode)

1247 {

1248 si_info_t *sii;

1249

1250 sii = SI_INFO(sih);

1251

1252 /* chipcommon cores prior to rev6 don't support dynamic clock control */

1253 if (sih->ccrev < 6)

1254 return false;

1255

1256 if (PCI_FORCEHT(sii))

1257 return mode == CLK_FAST;

1258

1259 return _si_clkctl_cc(sii, mode);

1260 }

1261

1262 /* clk control mechanism through chipcommon, no policy checking */

1263 static bool _si_clkctl_cc(si_info_t *sii, uint mode)

1264 {

1265 uint origidx = 0;

1266 chipcregs_t *cc;

1267 u32 scc;

1268 uint intr_val = 0;

1269 bool fast = SI_FAST(sii);

1270

1271 /* chipcommon cores prior to rev6 don't support dynamic clock control */

1272 if (sii->pub.ccrev < 6)

1273 return false;

1274

1275 if (!fast) {

1276 INTR_OFF(sii, intr_val);

1277 origidx = sii->curidx;

1278

1279 if ((sii->pub.bustype == SI_BUS) &&

1280 si_setcore(&sii->pub, MIPS33_CORE_ID, 0) &&

1281 (si_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10))

1282 goto done;

1283

1284 cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0);

1285 } else {

1286 cc = (chipcregs_t *) CCREGS_FAST(sii);

1287 if (cc == NULL)

1288 goto done;

1289 }

1290

1291 if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20))

1292 goto done;

1293

1294 switch (mode) {

1295 case CLK_FAST: /* FORCEHT, fast (pll) clock */

1296 if (sii->pub.ccrev < 10) {

1297 /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */

1298 si_clkctl_xtal(&sii->pub, XTAL, ON);

1299 SET_REG(&cc->slow_clk_ctl,

1300 (SCC_XC | SCC_FS | SCC_IP), SCC_IP);

1301 } else if (sii->pub.ccrev < 20) {

1302 OR_REG(&cc->system_clk_ctl, SYCC_HR);

1303 } else {

1304 OR_REG(&cc->clk_ctl_st, CCS_FORCEHT);

1305 }

1306

1307 /* wait for the PLL */

1308 if (PMUCTL_ENAB(&sii->pub)) {

1309 u32 htavail = CCS_HTAVAIL;

1310 SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)

1311 == 0), PMU_MAX_TRANSITION_DLY);

1312 } else {

1313 udelay(PLL_DELAY);

1314 }

1315 break;

1316

1317 case CLK_DYNAMIC: /* enable dynamic clock control */

1318 if (sii->pub.ccrev < 10) {

1319 scc = R_REG(&cc->slow_clk_ctl);

1320 scc &= ~(SCC_FS | SCC_IP | SCC_XC);

1321 if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)

1322 scc |= SCC_XC;

1323 W_REG(&cc->slow_clk_ctl, scc);

1324

1325 /* for dynamic control, we have to release our xtal_pu "force on" */

1326 if (scc & SCC_XC)

1327 si_clkctl_xtal(&sii->pub, XTAL, OFF);

1328 } else if (sii->pub.ccrev < 20) {

1329 /* Instaclock */

1330 AND_REG(&cc->system_clk_ctl, ~SYCC_HR);

1331 } else {

1332 AND_REG(&cc->clk_ctl_st, ~CCS_FORCEHT);

1333 }

1334 break;

1335

1336 default:

1337 break;

1338 }

1339

1340 done:

1341 if (!fast) {

1342 si_setcoreidx(&sii->pub, origidx);

1343 INTR_RESTORE(sii, intr_val);

1344 }

1345 return mode == CLK_FAST;

1346 }

1347

1348 /* Build device path. Support SI, PCI, and JTAG for now. */

1349 int si_devpath(si_t *sih, char *path, int size)

1350 {

1351 int slen;

1352

1353 if (!path || size <= 0)

1354 return -1;

1355

1356 switch (sih->bustype) {

1357 case SI_BUS:

1358 case JTAG_BUS:

1359 slen = snprintf(path, (size_t) size, "sb/%u/", si_coreidx(sih));

1360 break;

1361 case PCI_BUS:

1362 slen = snprintf(path, (size_t) size, "pci/%u/%u/",

1363 ((struct pci_dev *)((SI_INFO(sih))->pbus))->bus->number,

1364 PCI_SLOT(

1365 ((struct pci_dev *)((SI_INFO(sih))->pbus))->devfn));

1366 break;

1367

1368 #ifdef BCMSDIO

1369 case SDIO_BUS:

1370 SI_ERROR(("si_devpath: device 0 assumed\n"));

1371 slen = snprintf(path, (size_t) size, "sd/%u/", si_coreidx(sih));

1372 break;

1373 #endif

1374 default:

1375 slen = -1;

1376 break;

1377 }

1378

1379 if (slen < 0 || slen >= size) {

1380 path[0] = '\0';

1381 return -1;

1382 }

1383

1384 return 0;

1385 }

1386

1387 /* Get a variable, but only if it has a devpath prefix */

1388 char *si_getdevpathvar(si_t *sih, const char *name)

1389 {

1390 char varname[SI_DEVPATH_BUFSZ + 32];

1391

1392 si_devpathvar(sih, varname, sizeof(varname), name);

1393

1394 return getvar(NULL, varname);

1395 }

1396

1397 /* Get a variable, but only if it has a devpath prefix */

1398 int si_getdevpathintvar(si_t *sih, const char *name)

1399 {

1400 #if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)

1401 return getintvar(NULL, name);

1402 #else

1403 char varname[SI_DEVPATH_BUFSZ + 32];

1404

1405 si_devpathvar(sih, varname, sizeof(varname), name);

1406

1407 return getintvar(NULL, varname);

1408 #endif

1409 }

1410

1411 char *si_getnvramflvar(si_t *sih, const char *name)

1412 {

1413 return getvar(NULL, name);

1414 }

1415

1416 /* Concatenate the dev path with a varname into the given 'var' buffer

1417 * and return the 'var' pointer.

1418 * Nothing is done to the arguments if len == 0 or var is NULL, var is still returned.

1419 * On overflow, the first char will be set to '\0'.

1420 */

1421 static char *si_devpathvar(si_t *sih, char *var, int len, const char *name)

1422 {

1423 uint path_len;

1424

1425 if (!var || len <= 0)

1426 return var;

1427

1428 if (si_devpath(sih, var, len) == 0) {

1429 path_len = strlen(var);

1430

1431 if (strlen(name) + 1 > (uint) (len - path_len))

1432 var[0] = '\0';

1433 else

1434 strncpy(var + path_len, name, len - path_len - 1);

1435 }

1436

1437 return var;

1438 }

1439

1440 /* return true if PCIE capability exists in the pci config space */

1441 static __used bool si_ispcie(si_info_t *sii)

1442 {

1443 u8 cap_ptr;

1444

1445 if (sii->pub.bustype != PCI_BUS)

1446 return false;

1447

1448 cap_ptr = pcicore_find_pci_capability(sii->pbus, PCI_CAP_ID_EXP, NULL,

1449 NULL);

1450 if (!cap_ptr)

1451 return false;

1452

1453 return true;

1454 }

1455

1456 #ifdef BCMSDIO

1457 /* initialize the sdio core */

1458 void si_sdio_init(si_t *sih)

1459 {

1460 si_info_t *sii = SI_INFO(sih);

1461

1462 if (((sih->buscoretype == PCMCIA_CORE_ID) && (sih->buscorerev >= 8)) ||

1463 (sih->buscoretype == SDIOD_CORE_ID)) {

1464 uint idx;

1465 sdpcmd_regs_t *sdpregs;

1466

1467 /* get the current core index */

1468 idx = sii->curidx;

1469

1470 /* switch to sdio core */

1471 sdpregs = (sdpcmd_regs_t *) si_setcore(sih, PCMCIA_CORE_ID, 0);

1472 if (!sdpregs)

1473 sdpregs =

1474 (sdpcmd_regs_t *) si_setcore(sih, SDIOD_CORE_ID, 0);

1475

1476 SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d " "through SD core %d (%p)\n", sih->buscorerev, idx, sii->curidx, sdpregs));

1477

1478 /* enable backplane error and core interrupts */

1479 W_REG(&sdpregs->hostintmask, I_SBINT);

1480 W_REG(&sdpregs->sbintmask,

1481 (I_SB_SERR | I_SB_RESPERR | (1 << idx)));

1482

1483 /* switch back to previous core */

1484 si_setcoreidx(sih, idx);

1485 }

1486

1487 /* enable interrupts */

1488 bcmsdh_intr_enable(sii->pbus);

1489

1490 }

1491 #endif /* BCMSDIO */

1492

1493 bool si_pci_war16165(si_t *sih)

1494 {

1495 si_info_t *sii;

1496

1497 sii = SI_INFO(sih);

1498

1499 return PCI(sii) && (sih->buscorerev <= 10);

1500 }

1501

1502 void si_pci_up(si_t *sih)

1503 {

1504 si_info_t *sii;

1505

1506 sii = SI_INFO(sih);

1507

1508 /* if not pci bus, we're done */

1509 if (sih->bustype != PCI_BUS)

1510 return;

1511

1512 if (PCI_FORCEHT(sii))

1513 _si_clkctl_cc(sii, CLK_FAST);

1514

1515 if (PCIE(sii))

1516 pcicore_up(sii->pch, SI_PCIUP);

1517

1518 }

1519

1520 /* Unconfigure and/or apply various WARs when system is going to sleep mode */

1521 void si_pci_sleep(si_t *sih)

1522 {

1523 si_info_t *sii;

1524

1525 sii = SI_INFO(sih);

1526

1527 pcicore_sleep(sii->pch);

1528 }

1529

1530 /* Unconfigure and/or apply various WARs when going down */

1531 void si_pci_down(si_t *sih)

1532 {

1533 si_info_t *sii;

1534

1535 sii = SI_INFO(sih);

1536

1537 /* if not pci bus, we're done */

1538 if (sih->bustype != PCI_BUS)

1539 return;

1540

1541 /* release FORCEHT since chip is going to "down" state */

1542 if (PCI_FORCEHT(sii))

1543 _si_clkctl_cc(sii, CLK_DYNAMIC);

1544

1545 pcicore_down(sii->pch, SI_PCIDOWN);

1546 }

1547

1548 /*

1549 * Configure the pci core for pci client (NIC) action

1550 * coremask is the bitvec of cores by index to be enabled.

1551 */

1552 void si_pci_setup(si_t *sih, uint coremask)

1553 {

1554 si_info_t *sii;

1555 struct sbpciregs *pciregs = NULL;

1556 u32 siflag = 0, w;

1557 uint idx = 0;

1558

1559 sii = SI_INFO(sih);

1560

1561 if (sii->pub.bustype != PCI_BUS)

1562 return;

1563

1564 if (PCI(sii)) {

1565 /* get current core index */

1566 idx = sii->curidx;

1567

1568 /* we interrupt on this backplane flag number */

1569 siflag = si_flag(sih);

1570

1571 /* switch over to pci core */

1572 pciregs = (struct sbpciregs *)si_setcoreidx(sih, sii->pub.buscoreidx);

1573 }

1574

1575 /*

1576 * Enable sb->pci interrupts. Assume

1577 * PCI rev 2.3 support was added in pci core rev 6 and things changed..

1578 */

1579 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {

1580 /* pci config write to set this core bit in PCIIntMask */

1581 pci_read_config_dword(sii->pbus, PCI_INT_MASK, &w);

1582 w |= (coremask << PCI_SBIM_SHIFT);

1583 pci_write_config_dword(sii->pbus, PCI_INT_MASK, w);

1584 } else {

1585 /* set sbintvec bit for our flag number */

1586 si_setint(sih, siflag);

1587 }

1588

1589 if (PCI(sii)) {

1590 OR_REG(&pciregs->sbtopci2,

1591 (SBTOPCI_PREF | SBTOPCI_BURST));

1592 if (sii->pub.buscorerev >= 11) {

1593 OR_REG(&pciregs->sbtopci2,

1594 SBTOPCI_RC_READMULTI);

1595 w = R_REG(&pciregs->clkrun);

1596 W_REG(&pciregs->clkrun,

1597 (w | PCI_CLKRUN_DSBL));

1598 w = R_REG(&pciregs->clkrun);

1599 }

1600

1601 /* switch back to previous core */

1602 si_setcoreidx(sih, idx);

1603 }

1604 }

1605

1606 /*

1607 * Fixup SROMless PCI device's configuration.

1608 * The current core may be changed upon return.

1609 */

1610 int si_pci_fixcfg(si_t *sih)

1611 {

1612 uint origidx, pciidx;

1613 struct sbpciregs *pciregs = NULL;

1614 sbpcieregs_t *pcieregs = NULL;

1615 void *regs = NULL;

1616 u16 val16, *reg16 = NULL;

1617

1618 si_info_t *sii = SI_INFO(sih);

1619

1620 /* Fixup PI in SROM shadow area to enable the correct PCI core access */

1621 /* save the current index */

1622 origidx = si_coreidx(&sii->pub);

1623

1624 /* check 'pi' is correct and fix it if not */

1625 if (sii->pub.buscoretype == PCIE_CORE_ID) {

1626 pcieregs =

1627 (sbpcieregs_t *) si_setcore(&sii->pub, PCIE_CORE_ID, 0);

1628 regs = pcieregs;

1629 reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];

1630 } else if (sii->pub.buscoretype == PCI_CORE_ID) {

1631 pciregs = (struct sbpciregs *)si_setcore(&sii->pub, PCI_CORE_ID, 0);

1632 regs = pciregs;

1633 reg16 = &pciregs->sprom[SRSH_PI_OFFSET];

1634 }

1635 pciidx = si_coreidx(&sii->pub);

1636 val16 = R_REG(reg16);

1637 if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) {

1638 val16 =

1639 (u16) (pciidx << SRSH_PI_SHIFT) | (val16 &

1640 ~SRSH_PI_MASK);

1641 W_REG(reg16, val16);

1642 }

1643

1644 /* restore the original index */

1645 si_setcoreidx(&sii->pub, origidx);

1646

1647 pcicore_hwup(sii->pch);

1648 return 0;

1649 }

1650

1651 /* mask&set gpiocontrol bits */

1652 u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority)

1653 {

1654 uint regoff;

1655

1656 regoff = 0;

1657

1658 /* gpios could be shared on router platforms

1659 * ignore reservation if it's high priority (e.g., test apps)

1660 */

1661 if ((priority != GPIO_HI_PRIORITY) &&

1662 (sih->bustype == SI_BUS) && (val || mask)) {

1663 mask = priority ? (si_gpioreservation & mask) :

1664 ((si_gpioreservation | mask) & ~(si_gpioreservation));

1665 val &= mask;

1666 }

1667

1668 regoff = offsetof(chipcregs_t, gpiocontrol);

1669 return si_corereg(sih, SI_CC_IDX, regoff, mask, val);

1670 }

1671

1672 /* Return the size of the specified SOCRAM bank */

1673 static uint

1674 socram_banksize(si_info_t *sii, sbsocramregs_t *regs, u8 index,

1675 u8 mem_type)

1676 {

1677 uint banksize, bankinfo;

1678 uint bankidx = index | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT);

1679

1680 W_REG(&regs->bankidx, bankidx);

1681 bankinfo = R_REG(&regs->bankinfo);

1682 banksize =

1683 SOCRAM_BANKINFO_SZBASE * ((bankinfo & SOCRAM_BANKINFO_SZMASK) + 1);

1684 return banksize;

1685 }

1686

1687 /* Return the RAM size of the SOCRAM core */

1688 u32 si_socram_size(si_t *sih)

1689 {

1690 si_info_t *sii;

1691 uint origidx;

1692 uint intr_val = 0;

1693

1694 sbsocramregs_t *regs;

1695 bool wasup;

1696 uint corerev;

1697 u32 coreinfo;

1698 uint memsize = 0;

1699

1700 sii = SI_INFO(sih);

1701

1702 /* Block ints and save current core */

1703 INTR_OFF(sii, intr_val);

1704 origidx = si_coreidx(sih);

1705

1706 /* Switch to SOCRAM core */

1707 regs = si_setcore(sih, SOCRAM_CORE_ID, 0);

1708 if (!regs)

1709 goto done;

1710

1711 /* Get info for determining size */

1712 wasup = si_iscoreup(sih);

1713 if (!wasup)

1714 si_core_reset(sih, 0, 0);

1715 corerev = si_corerev(sih);

1716 coreinfo = R_REG(&regs->coreinfo);

1717

1718 /* Calculate size from coreinfo based on rev */

1719 if (corerev == 0)

1720 memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));

1721 else if (corerev < 3) {

1722 memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));

1723 memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;

1724 } else if ((corerev <= 7) || (corerev == 12)) {

1725 uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;

1726 uint bsz = (coreinfo & SRCI_SRBSZ_MASK);

1727 uint lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;

1728 if (lss != 0)

1729 nb--;

1730 memsize = nb * (1 << (bsz + SR_BSZ_BASE));

1731 if (lss != 0)

1732 memsize += (1 << ((lss - 1) + SR_BSZ_BASE));

1733 } else {

1734 u8 i;

1735 uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;

1736 for (i = 0; i < nb; i++)

1737 memsize +=

1738 socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);

1739 }

1740

1741 /* Return to previous state and core */

1742 if (!wasup)

1743 si_core_disable(sih, 0);

1744 si_setcoreidx(sih, origidx);

1745

1746 done:

1747 INTR_RESTORE(sii, intr_val);

1748

1749 return memsize;

1750 }

1751

1752 void si_chipcontrl_epa4331(si_t *sih, bool on)

1753 {

1754 si_info_t *sii;

1755 chipcregs_t *cc;

1756 uint origidx;

1757 u32 val;

1758

1759 sii = SI_INFO(sih);

1760 origidx = si_coreidx(sih);

1761

1762 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);

1763

1764 val = R_REG(&cc->chipcontrol);

1765

1766 if (on) {

1767 if (sih->chippkg == 9 || sih->chippkg == 0xb) {

1768 /* Ext PA Controls for 4331 12x9 Package */

1769 W_REG(&cc->chipcontrol, val |

1770 (CCTRL4331_EXTPA_EN |

1771 CCTRL4331_EXTPA_ON_GPIO2_5));

1772 } else {

1773 /* Ext PA Controls for 4331 12x12 Package */

1774 W_REG(&cc->chipcontrol,

1775 val | (CCTRL4331_EXTPA_EN));

1776 }

1777 } else {

1778 val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);

1779 W_REG(&cc->chipcontrol, val);

1780 }

1781

1782 si_setcoreidx(sih, origidx);

1783 }

1784

1785 /* Enable BT-COEX & Ex-PA for 4313 */

1786 void si_epa_4313war(si_t *sih)

1787 {

1788 si_info_t *sii;

1789 chipcregs_t *cc;

1790 uint origidx;

1791

1792 sii = SI_INFO(sih);

1793 origidx = si_coreidx(sih);

1794

1795 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);

1796

1797 /* EPA Fix */

1798 W_REG(&cc->gpiocontrol,

1799 R_REG(&cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);

1800

1801 si_setcoreidx(sih, origidx);

1802 }

1803

1804 /* check if the device is removed */

1805 bool si_deviceremoved(si_t *sih)

1806 {

1807 u32 w;

1808 si_info_t *sii;

1809

1810 sii = SI_INFO(sih);

1811

1812 switch (sih->bustype) {

1813 case PCI_BUS:

1814 pci_read_config_dword(sii->pbus, PCI_VENDOR_ID, &w);

1815 if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)

1816 return true;

1817 break;

1818 }

1819 return false;

1820 }

1821

1822 bool si_is_sprom_available(si_t *sih)

1823 {

1824 if (sih->ccrev >= 31) {

1825 si_info_t *sii;

1826 uint origidx;

1827 chipcregs_t *cc;

1828 u32 sromctrl;

1829

1830 if ((sih->cccaps & CC_CAP_SROM) == 0)

1831 return false;

1832

1833 sii = SI_INFO(sih);

1834 origidx = sii->curidx;

1835 cc = si_setcoreidx(sih, SI_CC_IDX);

1836 sromctrl = R_REG(&cc->sromcontrol);

1837 si_setcoreidx(sih, origidx);

1838 return sromctrl & SRC_PRESENT;

1839 }

1840

1841 switch (sih->chip) {

1842 case BCM4329_CHIP_ID:

1843 return (sih->chipst & CST4329_SPROM_SEL) != 0;

1844 case BCM4319_CHIP_ID:

1845 return (sih->chipst & CST4319_SPROM_SEL) != 0;

1846 case BCM4336_CHIP_ID:

1847 return (sih->chipst & CST4336_SPROM_PRESENT) != 0;

1848 case BCM4330_CHIP_ID:

1849 return (sih->chipst & CST4330_SPROM_PRESENT) != 0;

1850 case BCM4313_CHIP_ID:

1851 return (sih->chipst & CST4313_SPROM_PRESENT) != 0;

1852 case BCM4331_CHIP_ID:

1853 return (sih->chipst & CST4331_SPROM_PRESENT) != 0;

1854 default:

1855 return true;

1856 }

1857 }

1858

1859 bool si_is_otp_disabled(si_t *sih)

1860 {

1861 switch (sih->chip) {

1862 case BCM4329_CHIP_ID:

1863 return (sih->chipst & CST4329_SPROM_OTP_SEL_MASK) ==

1864 CST4329_OTP_PWRDN;

1865 case BCM4319_CHIP_ID:

1866 return (sih->chipst & CST4319_SPROM_OTP_SEL_MASK) ==

1867 CST4319_OTP_PWRDN;

1868 case BCM4336_CHIP_ID:

1869 return (sih->chipst & CST4336_OTP_PRESENT) == 0;

1870 case BCM4330_CHIP_ID:

1871 return (sih->chipst & CST4330_OTP_PRESENT) == 0;

1872 case BCM4313_CHIP_ID:

1873 return (sih->chipst & CST4313_OTP_PRESENT) == 0;

1874 /* These chips always have their OTP on */

1875 case BCM43224_CHIP_ID:

1876 case BCM43225_CHIP_ID:

1877 case BCM43421_CHIP_ID:

1878 case BCM43235_CHIP_ID:

1879 case BCM43236_CHIP_ID:

1880 case BCM43238_CHIP_ID:

1881 case BCM4331_CHIP_ID:

1882 default:

1883 return false;

1884 }

1885 }

1886

1887 bool si_is_otp_powered(si_t *sih)

1888 {

1889 if (PMUCTL_ENAB(sih))

1890 return si_pmu_is_otp_powered(sih);

1891 return true;

1892 }

1893

1894 void si_otp_power(si_t *sih, bool on)

1895 {

1896 if (PMUCTL_ENAB(sih))

1897 si_pmu_otp_power(sih, on);

1898 udelay(1000);

1899 }

1900