Peter Maydell [Tue, 10 Dec 2024 16:04:51 +0000 (16:04 +0000)]
target/arm: Move RME TLB insns to tlb-insns.c
Move the FEAT_RME specific TLB insns across to tlb-insns.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-10-peter.maydell@linaro.org
Peter Maydell [Tue, 10 Dec 2024 16:04:50 +0000 (16:04 +0000)]
target/arm: Move small helper functions to tlb-insns.c
The remaining functions that we temporarily made global are now
used only from callsits in tlb-insns.c; move them across and
make them file-local again.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-9-peter.maydell@linaro.org
Peter Maydell [Tue, 10 Dec 2024 16:04:49 +0000 (16:04 +0000)]
target/arm: Move the TLBI OS insns to tlb-insns.c.
Move the TLBI OS insns across to tlb-insns.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-8-peter.maydell@linaro.org
Peter Maydell [Tue, 10 Dec 2024 16:04:48 +0000 (16:04 +0000)]
target/arm: Move TLBI range insns
Move the TLBI invalidate-range insns across to tlb-insns.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-7-peter.maydell@linaro.org
Peter Maydell [Tue, 10 Dec 2024 16:04:47 +0000 (16:04 +0000)]
target/arm: Move AArch64 EL3 TLBI insns
Move the AArch64 EL3 TLBI insns from el3_cp_reginfo[] across
to tlb-insns.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-6-peter.maydell@linaro.org
Peter Maydell [Tue, 10 Dec 2024 16:04:46 +0000 (16:04 +0000)]
target/arm: Move the AArch64 EL2 TLBI insns
Move the AArch64 EL2 TLBI insn definitions that were
in el2_cp_reginfo[] across to tlb-insns.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-5-peter.maydell@linaro.org
Peter Maydell [Tue, 10 Dec 2024 16:04:45 +0000 (16:04 +0000)]
target/arm: Move AArch64 TLBI insns from v8_cp_reginfo[]
Move the AArch64 TLBI insns that are declared in v8_cp_reginfo[]
into tlb-insns.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-4-peter.maydell@linaro.org
Peter Maydell [Tue, 10 Dec 2024 16:04:44 +0000 (16:04 +0000)]
target/arm: Move TLBI insns for AArch32 EL2 to tlbi_insn_helper.c
Move the AArch32 TLBI insns for AArch32 EL2 to tlbi_insn_helper.c.
To keep this as an obviously pure code-movement, we retain the
same condition for registering tlbi_el2_cp_reginfo that we use for
el2_cp_reginfo. We'll be able to simplify this condition later,
since the need to define the reginfo for EL3-without-EL2 doesn't
apply for the TLBI ops specifically.
This move brings all the uses of tlbimva_hyp_write() and
tlbimva_hyp_is_write() back into a single file, so we can move those
also, and make them file-local again.
The helper alle1_tlbmask() is an exception to the pattern that we
only need to make these functions global temporarily, because once
this refactoring is complete it will be called by both code in
helper.c (vttbr_write()) and by code in tlb-insns.c. We therefore
put its prototype in a permanent home in internals.h.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-3-peter.maydell@linaro.org
Peter Maydell [Tue, 10 Dec 2024 16:04:43 +0000 (16:04 +0000)]
target/arm: Move some TLBI insns to their own source file
target/arm/helper.c is very large and unwieldy. One subset of code
that we can pull out into its own file is the cpreg arrays and
corresponding functions for the TLBI instructions.
Because these are instructions they are only relevant for TCG and we
can make the new file only be built for CONFIG_TCG.
In this commit we move the AArch32 instructions from:
not_v7_cp_reginfo[]
v7_cp_reginfo[]
v7mp_cp_reginfo[]
v8_cp_reginfo[]
into a new file target/arm/tcg/tlb-insns.c.
A few small functions are used both by functions we haven't yet moved
across and by functions we have already moved. We temporarily make
these global with a prototype in cpregs.h; when the move of all TLBI
insns is complete these will return to being file-local.
For CONFIG_TCG, this is just moving code around. For a KVM only
build, these cpregs will no longer be added to the cpregs hashtable
for the CPU. However this should not be a behaviour change, because:
* we never try to migration sync or otherwise include
ARM_CP_NO_RAW cpregs
* for migration we treat the kernel's list of system registers
as the authoritative one, so these TLBI insns were never
in it anyway
The no-tcg stub of define_tlb_insn_regs() therefore does nothing.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-2-peter.maydell@linaro.org
Brian Cain [Mon, 9 Dec 2024 18:12:42 +0000 (10:12 -0800)]
MAINTAINERS: correct my email address
Mea culpa, I don't know how I got this wrong in 2dfe93699c. Still
getting used to the new address, I suppose. Somehow I got it right in the
mailmap, though.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Message-id: 20241209181242.1434231-1-brian.cain@oss.qualcomm.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Fri, 6 Dec 2024 03:14:28 +0000 (21:14 -0600)]
target/arm: Use float_round_to_odd in helper_fcvtx_f64_to_f32
Softfloat has native support for round-to-odd. Use it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241206031428.78634-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Fri, 6 Dec 2024 16:04:09 +0000 (17:04 +0100)]
hw/nvram/fw_cfg: Pass QOM parent to fw_cfg_add_file_from_generator()
Currently fw_cfg_add_file_from_generator() is restricted
to command line created objects which reside in the
'/objects' QOM container. In order to extend to other
types of containers, pass the QOM parent by argument.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20241206181352.6836-3-philmd@linaro.org>
fw_cfg_add_from_generator() is adding a 'file' entry,
so rename as fw_cfg_add_file_from_generator() for
clarity. Besides, we might introduce generators for
other entry types.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20241206181352.6836-2-philmd@linaro.org>
Philippe Mathieu-Daudé [Mon, 25 Nov 2024 13:07:25 +0000 (14:07 +0100)]
hw/riscv/virt: Remove pointless GPEX_HOST() cast
No need to QOM-cast twice, since the intermediate value
is not used.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20241125140535.4526-7-philmd@linaro.org>
Dorjoy Chowdhury [Sat, 9 Nov 2024 12:30:39 +0000 (18:30 +0600)]
hw/core/eif: Use stateful qcrypto apis
We were storing the pointers to buffers in a GList due to lack of
stateful crypto apis and instead doing the final hash computation at
the end after we had all the necessary buffers. Now that we have the
stateful qcrypto apis available, we can instead update the hashes
inline in the read_eif_* functions which makes the code much simpler.
Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Reviewed-by: Alexander Graf <graf@amazon.com>
Message-ID: <20241109123039.24180-1-dorjoychy111@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:36 +0000 (10:30 -0600)]
target/arm: Convert FCVTL to decodetree
Remove lookup_disas_fn, handle_2misc_widening,
disas_simd_two_reg_misc, disas_data_proc_simd,
disas_data_proc_simd_fp, disas_a64_legacy, as
this is the final insn to be converted.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-70-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:35 +0000 (10:30 -0600)]
target/arm: Convert URECPE and URSQRTE to decodetree
Remove handle_2misc_reciprocal as these were the last
insns decoded by that function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-69-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-68-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:33 +0000 (10:30 -0600)]
target/arm: Convert FRECPE, FRECPX, FRSQRTE to decodetree
Remove disas_simd_scalar_two_reg_misc and
disas_simd_two_reg_misc_fp16 as these were the
last insns decoded by those functions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-67-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:32 +0000 (10:30 -0600)]
target/arm: Convert handle_2misc_fcmp_zero to decodetree
This includes FCMEQ, FCMGT, FCMGE, FCMLT, FCMLE.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-66-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:31 +0000 (10:30 -0600)]
target/arm: Convert FCVT* (vector, integer) to decodetree
Remove handle_2misc_64 as these were the last insns decoded
by that function. Remove helper_advsimd_f16to[su]inth as unused;
we now always go through helper_vfp_to[su]hh or a specialized
vector function instead.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-65-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:30 +0000 (10:30 -0600)]
target/arm: Convert FCVTZ[SU] (vector, fixed-point) to decodetree
Remove handle_simd_shift_fpint_conv and disas_simd_shift_imm
as these were the last insns decoded by those functions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-64-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:29 +0000 (10:30 -0600)]
target/arm: Convert [US]CVTF (vector) to decodetree
Remove handle_simd_intfp_conv and handle_simd_shift_intfp_conv
as these were the last insns decoded by those functions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-63-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:28 +0000 (10:30 -0600)]
target/arm: Rename helper_gvec_vcvt_[hf][su] with _rz
Emphasize that these functions use round-to-zero mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-62-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:27 +0000 (10:30 -0600)]
target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree
Remove disas_simd_scalar_shift_imm as these were the
last insns decoded by that function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-61-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:26 +0000 (10:30 -0600)]
target/arm: Convert [US]CVTF (vector, integer) scalar to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-60-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:25 +0000 (10:30 -0600)]
target/arm: Convert FCVT* (vector, fixed-point) scalar to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-59-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:24 +0000 (10:30 -0600)]
target/arm: Convert FCVT* (vector, integer) scalar to decodetree
Arm silliness with naming, the scalar insns described
as part of the vector instructions, as separate from
the "regular" scalar insns which output to general registers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-58-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:23 +0000 (10:30 -0600)]
target/arm: Convert FRINT* (vector) to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-57-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:22 +0000 (10:30 -0600)]
target/arm: Convert FSQRT (vector) to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-56-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:21 +0000 (10:30 -0600)]
target/arm: Convert FABS, FNEG (vector) to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-55-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Move the current implementation out of translate-neon.c,
and extend to handle all element sizes.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-54-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:19 +0000 (10:30 -0600)]
target/arm: Convert SHLL to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-53-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:18 +0000 (10:30 -0600)]
target/arm: Convert FCVTXN to decodetree
Remove handle_2misc_narrow as this was the last insn decoded
by that function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-52-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:17 +0000 (10:30 -0600)]
target/arm: Convert FCVTN, BFCVTN to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-51-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:16 +0000 (10:30 -0600)]
target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-50-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:15 +0000 (10:30 -0600)]
target/arm: Introduce clear_vec
In a couple of places, clearing the entire vector before storing one
element is the easiest solution. Wrap that into a helper function.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-49-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
These have generic equivalents: tcg_gen_vec_{add,sub}{16,32}_i64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-48-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:13 +0000 (10:30 -0600)]
target/arm: Convert handle_2misc_pairwise to decodetree
This includes SADDLP, UADDLP, SADALP, UADALP.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-47-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:12 +0000 (10:30 -0600)]
target/arm: Introduce gen_gvec_{s,u}{add,ada}lp
Pairwise addition with and without accumulation.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-46-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:11 +0000 (10:30 -0600)]
target/arm: Move helper_neon_addlp_{s8, s16} to neon_helper.c
Move from helper-a64.c to neon_helper.c so that these
functions are available for arm32 code as well.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-45-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:10 +0000 (10:30 -0600)]
target/arm: Convert handle_rev to decodetree
This includes REV16, REV32, REV64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-44-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:09 +0000 (10:30 -0600)]
target/arm: Introduce gen_gvec_rev{16,32,64}
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-43-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:08 +0000 (10:30 -0600)]
target/arm: Convert CMGT, CMGE, GMLT, GMLE, CMEQ (zero) to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-42-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:07 +0000 (10:30 -0600)]
target/arm: Convert CNT, NOT, RBIT (vector) to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-41-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:06 +0000 (10:30 -0600)]
target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit
Add gvec interfaces for CNT and RBIT operations.
Use ctpop8 for CNT and revbit+bswap for RBIT.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-40-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:05 +0000 (10:30 -0600)]
target/arm: Convert CLS, CLZ (vector) to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-39-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:04 +0000 (10:30 -0600)]
target/arm: Introduce gen_gvec_cls, gen_gvec_clz
Add gvec interfaces for CLS and CLZ operations.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-38-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:03 +0000 (10:30 -0600)]
target/arm: Convert ABS, NEG to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-37-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:02 +0000 (10:30 -0600)]
target/arm: Convert SQABS, SQNEG to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:01 +0000 (10:30 -0600)]
target/arm: Convert handle_fmov to decodetree
Remove disas_fp_int_conv and disas_data_proc_fp as these
were the last insns decoded by those functions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-35-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:30:00 +0000 (10:30 -0600)]
target/arm: Convert FJCVTZS to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:59 +0000 (10:29 -0600)]
target/arm: Convert handle_fpfpcvt to decodetree
This includes SCVTF, UCVTF, FCVT{N,P,M,Z,A}{S,U}.
Remove disas_fp_fixed_conv as those were the last insns
decoded by that function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-33-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:58 +0000 (10:29 -0600)]
target/arm: Convert FCVT (scalar) to decodetree
Remove handle_fp_fcvt and disas_fp_1src as these were
the last insns decoded by those functions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:57 +0000 (10:29 -0600)]
target/arm: Convert FRINT{32, 64}[ZX] (scalar) to decodetree
Remove handle_fp_1src_single and handle_fp_1src_double as
these were the last insns decoded by those functions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:56 +0000 (10:29 -0600)]
target/arm: Convert BFCVT to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:55 +0000 (10:29 -0600)]
target/arm: Convert FRINT[NPMSAXI] (scalar) to decodetree
Remove handle_fp_1src_half as these were the last insns
decoded by that function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:54 +0000 (10:29 -0600)]
target/arm: Convert FSQRT (scalar) to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:53 +0000 (10:29 -0600)]
target/arm: Remove helper_sqrt_f16
This function is identical with helper_vfp_sqrth.
Replace all uses.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:52 +0000 (10:29 -0600)]
target/arm: Pass fpstatus to vfp_sqrt*
Pass fpstatus not env, like most other fp helpers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:51 +0000 (10:29 -0600)]
target/arm: Convert FMOV, FABS, FNEG (scalar) to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:50 +0000 (10:29 -0600)]
target/arm: Fix decode of fp16 vector fabs, fneg, fsqrt
These opcodes are only supported as vector operations,
not as advsimd scalar. Set only_in_vector, and remove
the unreachable implementation of scalar fneg.
Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20241211163036.2297116-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:49 +0000 (10:29 -0600)]
target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:48 +0000 (10:29 -0600)]
target/arm: Introduce fp_access_check_vector_hsd
Provide a simple way to check for float64, float32, and float16
support vs vector width, as well as the fpu enabled.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:47 +0000 (10:29 -0600)]
target/arm: Introduce fp_access_check_scalar_hsd
Provide a simple way to check for float64, float32,
and float16 support, as well as the fpu enabled.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:46 +0000 (10:29 -0600)]
target/arm: Convert disas_cond_select to decodetree
This includes CSEL, CSINC, CSINV, CSNEG. Remove disas_data_proc_reg,
as these were the last insns decoded by that function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:45 +0000 (10:29 -0600)]
target/arm: Convert CCMP, CCMN to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:44 +0000 (10:29 -0600)]
target/arm: Convert SETF8, SETF16 to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:43 +0000 (10:29 -0600)]
target/arm: Convert RMIF to decodetree
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:42 +0000 (10:29 -0600)]
target/arm: Convert disas_adc_sbc to decodetree
This includes ADC, SBC, ADCS, SBCS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:41 +0000 (10:29 -0600)]
target/arm: Convert disas_data_proc_3src to decodetree
This includes MADD, MSUB, SMADDL, SMSUBL, UMADDL, UMSUBL, SMULH, UMULH.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:40 +0000 (10:29 -0600)]
target/arm: Convert disas_add_sub_reg to decodetree
This includes ADD, SUB, ADDS, SUBS (shifted register).
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:39 +0000 (10:29 -0600)]
target/arm: Convert disas_add_sub_ext_reg to decodetree
This includes ADD, SUB, ADDS, SUBS (extended register).
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:38 +0000 (10:29 -0600)]
target/arm: Convert disas_logic_reg to decodetree
This includes AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS (shifted reg).
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:37 +0000 (10:29 -0600)]
target/arm: Convert XPAC[ID] to decodetree
Remove disas_data_proc_1src, as these were the last insns
decoded by that function.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:36 +0000 (10:29 -0600)]
target/arm: Convert PAC[ID]*, AUT[ID]* to decodetree
This includes PACIA, PACIZA, PACIB, PACIZB, PACDA, PACDZA, PACDB,
PACDZB, AUTIA, AUTIZA, AUTIB, AUTIZB, AUTDA, AUTDZA, AUTDB, AUTDZB.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:35 +0000 (10:29 -0600)]
target/arm: Convert CLZ, CLS to decodetree
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:34 +0000 (10:29 -0600)]
target/arm: Convert RBIT, REV16, REV32, REV64 to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:33 +0000 (10:29 -0600)]
target/arm: Convert PACGA to decodetree
Remove disas_data_proc_2src, as this was the last insn
decoded by that function.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:32 +0000 (10:29 -0600)]
target/arm: Convert SUBP, IRG, GMI to decodetree
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:31 +0000 (10:29 -0600)]
target/arm: Convert CRC32, CRC32C to decodetree
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:30 +0000 (10:29 -0600)]
target/arm: Convert LSLV, LSRV, ASRV, RORV to decodetree
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:29 +0000 (10:29 -0600)]
target/arm: Convert UDIV, SDIV to decodetree
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Wed, 11 Dec 2024 16:29:28 +0000 (10:29 -0600)]
target/arm: Add section labels for "Data Processing (register)"
At the same time, use ### to separate 3rd-level sections.
We already use ### for 4.1.92 Data Processing (immediate),
but not the two following two third-level sections:
4.1.93 Branches, and 4.1.94 Loads and stores.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Anton Johansson [Fri, 6 Dec 2024 16:01:03 +0000 (17:01 +0100)]
target/hexagon: Make HVX vector args. restrict *
Adds restrict qualifier to HVX pointer arguments. This will allow the
compiler to produce better optimized code, as input vectors are now
assumed not to alias, and no runtime aliasing checks will be required.
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Anton Johansson [Fri, 6 Dec 2024 16:01:02 +0000 (17:01 +0100)]
target/hexagon: Use argparse in all python scripts
QOL commit, all the various gen_* python scripts take a large set
arguments where order is implicit. Using argparse we also get decent
error messages if a field is missing or too many are added.
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain [Tue, 27 Aug 2024 00:26:30 +0000 (17:26 -0700)]
target/hexagon: rename HEX_EXCP_*=>HEX_CAUSE_*
The values previously used for "HEX_EXCP_*" were the cause code
definitions and not the event numbers. So in this commit, we update
the names to reflect the cause codes. In HEX_EVENT_TRAP0's case, we add
a new "HEX_EVENT_*" with the correct event number.
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Stefan Hajnoczi [Thu, 12 Dec 2024 23:45:39 +0000 (18:45 -0500)]
Merge tag 'pull-tcg-20241212' of https://gitlab.com/rth7680/qemu into staging
tcg: Reset free_temps before tcg_optimize
tcg/riscv: Fix StoreStore barrier generation
include/exec: Introduce fpst alias in helper-head.h.inc
target/sparc: Use memcpy() and remove memcpy32()
* tag 'pull-tcg-20241212' of https://gitlab.com/rth7680/qemu:
target/sparc: Use memcpy() and remove memcpy32()
include/exec: Introduce fpst alias in helper-head.h.inc
tcg/riscv: Fix StoreStore barrier generation
tcg: Reset free_temps before tcg_optimize
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Thu, 12 Dec 2024 23:45:09 +0000 (18:45 -0500)]
Merge tag 'qtest-20241212-pull-request' of https://gitlab.com/farosas/qemu into staging
Qtest pull request
- TIMEOUT_MULTIPLIER setting to allow tests to take longer when asan is enabled
- New qtest_system_reset() wrapper to properly wait for a system reset
- Split of migration-test.c into multiple files under qtest/migration/
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# gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown]
# gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D
* tag 'qtest-20241212-pull-request' of https://gitlab.com/farosas/qemu: (22 commits)
tests/qtest/migration: Split validation tests + misc
tests/qtest/migration-test: Fix and enable test_ignore_shared
tests/qtest/migration: Split CPR tests
tests/qtest/migration: Split precopy tests
tests/qtest/migration: Split file tests
tests/qtest/migration: Split postcopy tests
tests/qtest/migration: Split compression tests from migration-test.c
tests/qtest/migration: Split TLS tests from migration-test.c
tests/qtest/migration: Move common test code
tests/qtest/migration: Isolate test initialization
tests/qtest/migration: Move kvm_dirty_ring_supported to utils
tests/qtest/migration: Move ufd_version_check to utils
tests/qtest/migration: Rename migration-helpers.c
tests/qtest/migration: Move qmp helpers to a separate file
tests/qtest/migration: Move bootfile code to its own file
tests/migration: Disambiguate guestperf vs. a-b
tests/qtest/migration: Stop calling everything "test"
tests/qtest/migration: Standardize hook names
tests/qtest: Use qtest_system_reset_nowait() where appropriate
tests/qtest: Use qtest_system_reset() instead of open-coded versions
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Thu, 12 Dec 2024 23:40:32 +0000 (18:40 -0500)]
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* rust: better integration with clippy, rustfmt and rustdoc
* rust: interior mutability types
* rust: add a bit operations module
* rust: first part of QOM rework
* kvm: remove unnecessary #ifdef
* clock: small cleanups, improve handling of Clock lifetimes
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (49 commits)
rust: qom: change the parent type to an associated type
rust: qom: split ObjectType from ObjectImpl trait
rust: qom: move bridge for TypeInfo functions out of pl011
rust: qdev: move bridge for realize and reset functions out of pl011
rust: qdev: move device_class_init! body to generic function, ClassInitImpl implementation to macro
rust: qom: move ClassInitImpl to the instance side
rust: qom: convert type_info! macro to an associated const
rust: qom: rename Class trait to ClassInitImpl
rust: qom: add default definitions for ObjectImpl
rust: add a bit operation module
rust: add bindings for interrupt sources
rust: define prelude
rust: cell: add BQL-enforcing RefCell variant
rust: cell: add BQL-enforcing Cell variant
bql: check that the BQL is not dropped within marked sections
qom/object: Remove type_register()
script/codeconverter/qom_type_info: Deprecate MakeTypeRegisterStatic and MakeTypeRegisterNotStatic
ui: Replace type_register() with type_register_static()
target/xtensa: Replace type_register() with type_register_static()
target/sparc: Replace type_register() with type_register_static()
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Thu, 12 Dec 2024 23:40:08 +0000 (18:40 -0500)]
Merge tag 'pull-target-arm-20241211' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
* fpu: Make muladd NaN handling runtime-selected, not compile-time
* fpu: Make default NaN pattern runtime-selected, not compile-time
* fpu: Minor NaN-related cleanups
* MAINTAINERS: email address updates
* tag 'pull-target-arm-20241211' of https://git.linaro.org/people/pmaydell/qemu-arm: (72 commits)
MAINTAINERS: Add correct email address for Vikram Garhwal
MAINTAINERS: update email address for Leif Lindholm
softfloat: Replace WHICH with RET in parts_pick_nan
softfloat: Sink frac_cmp in parts_pick_nan until needed
softfloat: Share code between parts_pick_nan cases
softfloat: Inline pickNaN
softfloat: Use parts_pick_nan in propagateFloatx80NaN
softfloat: Move propagateFloatx80NaN to softfloat.c
softfloat: Pad array size in pick_nan_muladd
softfloat: Remove which from parts_pick_nan_muladd
softfloat: Use goto for default nan case in pick_nan_muladd
softfloat: Inline pickNaNMulAdd
fpu: Remove default handling for dnan_pattern
target/tricore: Set default NaN pattern explicitly
target/riscv: Set default NaN pattern explicitly
target/hexagon: Set default NaN pattern explicitly
target/xtensa: Set default NaN pattern explicitly
target/sparc: Set default NaN pattern explicitly
target/s390x: Set default NaN pattern explicitly
target/rx: Set default NaN pattern explicitly
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Thu, 12 Dec 2024 23:39:19 +0000 (18:39 -0500)]
Merge tag 'pull-request-2024-12-11' of https://gitlab.com/thuth/qemu into staging
* Add compat machines for QEMU 10.0
* Add s390x CPU model for the gen17 mainframe
* Convert some more avocado tests to the new functional framework
* Some minor clean-ups for functional tests
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