Stefan Riedmueller [Mon, 29 Mar 2021 13:01:03 +0000 (15:01 +0200)]
ARM: dts: imx6: pbab01: Set vmmc supply for both SD interfaces
Setting the vmmc supplies is crucial since otherwise the supplying
regulators get disabled and the SD interfaces are no longer powered
which leads to system failures if the system is booted from that SD
interface.
Fixes: 1e44d3f880d5 ("ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module") Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stefan Riedmueller [Mon, 29 Mar 2021 13:01:02 +0000 (15:01 +0200)]
ARM: dts: imx6: pbab01: Set USB OTG port to peripheral
Due to a hardware bug preventing the correct detection if the ID pin
the USB OTG port cannot be used in otg mode. It can either be set to
host or peripheral. Set it to peripheral so vbus is disabled by default.
Stefan Riedmueller [Mon, 29 Mar 2021 13:01:01 +0000 (15:01 +0200)]
ARM: dts: imx6: pfla02: Fix USB vbus enable pinmuxing
The pinmuxing for the enable pin of the usbh1 node is wrong. It needs to
be muxed as GPIO. While at it, move the pinctrl to the vbus regulator
since it is actually the regulator enable pin.
Oliver Stäbler [Wed, 24 Mar 2021 13:28:41 +0000 (14:28 +0100)]
arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0
Fix address of the pad control register
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2. This seems
to be a typo but it leads to an exception when pinctrl is applied due to
wrong memory address access.
Signed-off-by: Oliver Stäbler <oliver.staebler@bytesatwork.ch> Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm") Fixes: 748f908cc882 ("arm64: add basic DTS for i.MX8MQ") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The failsafe partitions for the DP firmware and for AT-F are unused. If
AT-F will ever be supported in the failsafe mode, then it will be a FIT
image. Thus fold the unused partitions into the failsafe bootloader one
to have enough storage if the bootloader image will grow.
While at it, remove the reserved partition. It served no purpose other
than having no hole in the map.
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Move the MTD partitions to the partitions subnode. This is the new way
to specify the partitions, see
Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fabio Estevam [Thu, 18 Mar 2021 11:13:30 +0000 (08:13 -0300)]
arm64: dts: imx8mp-evk: Improve the Ethernet PHY description
According to the datasheet RTL8211, it must be asserted low for at least
10ms and at least 72ms "for internal circuits settling time" before
accessing the PHY registers.
Sebastian Krzyszkowiak [Mon, 15 Mar 2021 08:35:30 +0000 (09:35 +0100)]
arm64: dts: imx8mq-librem5-r3: Mark buck3 as always on
Commit 99e71c029213 ("arm64: dts: imx8mq-librem5: Don't mark buck3 as always on")
removed always-on marking from GPU regulator, which is great for power
saving - however it introduces additional i2c0 traffic which can be deadly
for devices from the Dogwood batch.
To workaround the i2c0 shutdown issue on Dogwood, this commit marks
buck3 as always-on again - but only for Dogwood (r3).
Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.
Vladimir Oltean [Mon, 8 Mar 2021 13:08:34 +0000 (15:08 +0200)]
arm64: dts: ls1028a: set up the real link speed for ENETC port 2
In NXP LS1028A there is a MAC-to-MAC internal link between enetc_port2
and mscc_felix_port4. This link operates at 2.5Gbps and is described as
such for the mscc_felix_port4 node.
The reason for the discrepancy is a limitation in the PHY library
support for fixed-link nodes. Due to the fact that the PHY library
registers a software PHY which emulates the clause 22 register map, the
drivers/net/phy/fixed_phy.c driver only supports speeds up to 1Gbps.
The mscc_felix_port4 node is probed by DSA, which does not use the PHY
library directly, but phylink, and phylink has a different representation
for fixed-link nodes, one that does not have the limitation of not being
able to represent speeds > 1Gbps.
Since the enetc driver was converted to phylink too as of commit 71b77a7a27a3 ("enetc: Migrate to PHYLINK and PCS_LYNX"), the limitation
has been practically lifted there too, and we can describe the real link
speed in the device tree now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Dong Aisheng [Mon, 8 Mar 2021 03:14:30 +0000 (11:14 +0800)]
arm64: dts: imx: add imx8qm mek support
The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53
proccessor with powerful graphic and multimedia features.
This patch adds i.MX8QuadMax MEK board support.
Note that MX8QM needs a special workaround for TLB flush due to a SoC
errata, otherwise there may be random crash if enable both clusters of
A72 and A53. As the errata workaround is still not in mainline, so we
disable A72 cluster first for MX8QM MEK.
Dong Aisheng [Mon, 8 Mar 2021 03:14:29 +0000 (11:14 +0800)]
arm64: dts: imx: add imx8qm common dts file
The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53
proccessor with powerful graphic and multimedia features. It uses
the same architecture as MX8QXP, so many SS can be reused.
This patch adds i.MX8QuadMax SoC dtsi file.
Dong Aisheng [Mon, 8 Mar 2021 03:14:28 +0000 (11:14 +0800)]
arm64: dts: imx8qm: add dma ss support
The DMA SS of MX8QM is mostly the same as the DMA part in MX8QXP ADMA SS
while it has one more instance for each of LPUART, ADC and LPI2C. And unlike
MX8QXP that flexcan clocks are shared between multiple CAN instances,
MX8QM has separate flexcan clock slice.
So we reuse the most part of common imx8-ss-dma.dtsi and add new things
based on it.
Dong Aisheng [Mon, 8 Mar 2021 03:14:26 +0000 (11:14 +0800)]
arm64: dts: imx8qm: add conn ss support
The CONN SS of MX8QM is mostly the same as MX8QXP except it has one more
USB HSIC module support. So we can fully reuse the exist CONN SS dtsi.
Add <soc>-ss-conn.dtsi with compatible string updated according to
imx8-ss-conn.dtsi.
Dong Aisheng [Mon, 8 Mar 2021 03:14:25 +0000 (11:14 +0800)]
arm64: dts: imx8qm: add lsio ss support
The LSIO SS of MX8QM is exactly the same as MX8QXP. So we can fully
reuse the exist LSIO SS dtsi. Add <soc>-ss-lsio.dtsi with compatible
string updated according to imx8-ss-lsio.dtsi.
Dong Aisheng [Mon, 8 Mar 2021 03:14:19 +0000 (11:14 +0800)]
arm64: dts: imx8qxp: orginize dts in subsystems
MX8 SoC is comprised of a few HW subsystems while some of them can be
reused in the different SoCs. So let's re-orginize them into subsystems
in device tree as well for the possible reuse of the common part.
Note, as there's still no devices of hsio subsys, so removed it
first instead of creating a subsys headfile with no devices.
They will be added back when new devices added.
SCU clock depends on SCU Power domain. Moving scu pd node before
scu clock can save a hundred of defer probes of all system devices
which depends on power domain and clocks.
Alistair Francis [Mon, 22 Mar 2021 13:09:27 +0000 (09:09 -0400)]
ARM: imx7d-remarkable2: Initial device tree for reMarkable2
The reMarkable2 (https://remarkable.com) is an e-ink tablet based on
the imx7d SoC.
This commit is based on the DTS provide by reMarkable but ported to the
latest kernel (instead of 4.14). I have removed references to
non-upstream devices and have changed the UART so that the console can
be accessed without having to open up the device via the OTG pogo pins.
Currently the kernel boots, but there is no support for the display.
WiFi is untested (no display or UART RX makes it hard to test), but
should work with the current upstream driver. As it's untested it's not
included in this commit.
Signed-off-by: Alistair Francis <alistair@alistair23.me> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Ulf Hansson [Wed, 17 Mar 2021 09:31:17 +0000 (10:31 +0100)]
firmware: imx: scu-pd: Update comments for single global power domain
Since the introduction of the PM domain support for the scu-pd, the genpd
framework has been continuously improved. More preciously, using a single
global power domain can quite easily be deployed for imx platforms.
To avoid confusions, let's therefore make an update to the comments about
the missing pieces.
dillon min [Wed, 17 Mar 2021 15:45:09 +0000 (23:45 +0800)]
ARM: dts: imx6ull: fix ubi filesystem mount failed
For NAND Ecc layout, there is a dependency from old kernel's nand driver
setting and current. if old kernel use 4 bit ecc , we should use 4 bit
in new kernel either. else will run into following error at filesystem
mounting.
So, enable fsl,use-minimum-ecc from device tree, to fix this mismatch
[ 9.449265] ubi0: scanning is finished
[ 9.463968] ubi0 warning: ubi_io_read: error -74 (ECC error) while reading
22528 bytes from PEB 513:4096, read only 22528 bytes, retry
[ 9.486940] ubi0 warning: ubi_io_read: error -74 (ECC error) while reading
22528 bytes from PEB 513:4096, read only 22528 bytes, retry
[ 9.509906] ubi0 warning: ubi_io_read: error -74 (ECC error) while reading
22528 bytes from PEB 513:4096, read only 22528 bytes, retry
[ 9.532845] ubi0 error: ubi_io_read: error -74 (ECC error) while reading
22528 bytes from PEB 513:4096, read 22528 bytes
Fabio Estevam [Fri, 12 Mar 2021 11:37:46 +0000 (08:37 -0300)]
ARM: imx6ul-14x14-evk: Do not reset the Ethernet PHYs independently
The imx6ul-evk board designer took the bad decision to tie the
two Ethernet PHY reset lines together. This prevents one Ethernet
interface to work while the other one is brought down. For example:
# ifconfig eth0 down
# [ 279.386551] fec 2188000.ethernet eth1: Link is Down
Bringing eth0 interface down also causes eth1 to be down.
The Ethernet reset lines comes from the IO expander and both come in
logic level 0 by default.
To fix this issue, remove the Ethernet PHY reset descriptions from
its respective PHY nodes and force both Ethernet PHY lines to be at
logic level 1 via gpio-hog.
Remove the unnecessary #address-cells/#size-cells to avoid warnings
from W=1 build like this:
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi:33.12-78.4: Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
[fabio: Make the warning messages more succint] Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Remove the unnecessary #address-cells/#size-cells and rename the node
names to fix the following W=1 dtc warnings:
arch/arm/boot/dts/imx6dl-plybas.dts:26.13-30.5: Warning (unit_address_vs_reg): /gpio_keys/button@20: node has a unit name, but no reg or ranges property
arch/arm/boot/dts/imx6dl-plybas.dts:32.13-36.5: Warning (unit_address_vs_reg): /gpio_keys/button@21: node has a unit name, but no reg or ranges property
arch/arm/boot/dts/imx6dl-plybas.dts:20.12-37.4: Warning (avoid_unnecessary_addr_size): /gpio_keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Ian Ray [Mon, 8 Mar 2021 15:18:29 +0000 (16:18 +0100)]
ARM: dts: imx: bx50v3: Define GPIO line names
Define GPIO line names for b450v3, b650v3, and b850v3.
Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Sebastian Reichel [Mon, 8 Mar 2021 15:18:27 +0000 (16:18 +0100)]
ARM: dts: imx6q-ba16: improve PHY information
Add PHY voltage supply information fixing the following kernel message:
2188000.ethernet supply phy not found, using dummy regulator
Also add PHY clock information to avoid depending on the bootloader
programming correct values.
The bootloader also sets some reserved registers in the PHY as
advised by Qualcomm, which is not supported by the bindings/kernel
driver, so the reset GPIO has not been added intentionally.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Philippe Schenker [Thu, 4 Mar 2021 09:31:39 +0000 (10:31 +0100)]
ARM: dts: colibri-imx6ull: Change drive strength for usdhc2
The current setting reflects about 86 Ohms of source-impedance
on the SDIO signals where the WiFi board is hooked up. PCB traces are
routed with 50 Ohms impedance and there are no serial resistors on
those traces.
This commit changes the source-impedance to 52 Ohms to better match our
hardware design.
The impedances given in this commit message refer to 3.3V operation.
Alexander Shiyan [Mon, 15 Feb 2021 05:20:19 +0000 (08:20 +0300)]
ARM: dts: imx6ql-pfla02: Move "hog" pins into corresponded pin groups
Move the "hog" pins to the corresponding pin groups for SPI, ENET, PMIC,
LEDs, so that these pins can be used for different purposes when the
respective drivers are disabled.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Horia Geantă [Sun, 7 Mar 2021 20:47:35 +0000 (22:47 +0200)]
arm64: dts: ls1046a: mark crypto engine dma coherent
Crypto engine (CAAM) on LS1046A platform is configured HW-coherent,
mark accordingly the DT node.
As reported by Greg and Sascha, and explained by Robin, lack of
"dma-coherent" property for an IP that is configured HW-coherent
can lead to problems, e.g. on v5.11:
Marek Vasut [Sun, 28 Feb 2021 21:18:33 +0000 (22:18 +0100)]
arm64: dts: imx8mp: add eqos node and alias
Add EQOS GMAC node per Documentation/devicetree/bindings/net/imx-dwmac.txt ,
leave out the nvmem entries as that is not yet available, so the MAC has to
be passed in via DT by the bootloader.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Heiko Schocher <hs@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Jagan Teki [Thu, 25 Feb 2021 19:24:01 +0000 (00:54 +0530)]
arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM
i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini
from Engicam.
General features:
- NXP i.MX8M Mini
- Up to 2GB LDDR4
- 8/16GB eMMC
- Gigabit Ethernet
- USB 2.0 Host/OTG
- PCIe Gen2 interface
- I2S
- MIPI DSI to LVDS
- rest of i.MX8M Mini features
i.Core MX8M Mini needs to mount on top of Engicam baseboards
for creating complete platform solutions.
Add support for it.
Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Guido Günther [Sun, 21 Feb 2021 11:07:11 +0000 (12:07 +0100)]
arm64: dts: librem5-devkit: Move headphone detection to sound card
This allows for automatic output source switching in userspace. Enable
the pullup on the GPIO to actually make it trigger and mark it as
active-high since detection is reversed otherwise.
Guido Günther [Sun, 21 Feb 2021 11:07:06 +0000 (12:07 +0100)]
arm64: dts: librem5-devkit: Use a less generic codec name
The codec is currently named after the chip but it should be named like
the device itself since otherwise it's impossible to distinguish it from
other devices using the same codec (e.g. in alsa's UCM).
Michael Walle [Tue, 9 Feb 2021 00:52:59 +0000 (01:52 +0100)]
arm64: dts: ls1028a: add interrupt to Root Complex Event Collector
The legacy interrupt INT_A is hardwired to the event collector. RCEC is
bascially supported starting with v5.11. Having a correct interrupt, will
make RCEC at least probe correctly.
There are still issues with how RCEC is implemented in the RCiEP on the
LS1028A. RCEC will report an error, but it cannot find the correct
subdevice.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fabio Estevam [Mon, 8 Feb 2021 14:33:27 +0000 (11:33 -0300)]
arm64: dts: imx8mm-nitrogen-r2: Pass the i2c3 unit name
Pass the i2c3 unit name to fix the following W=1 build warning:
arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts:159.8-172.5: Warning (unit_address_vs_reg): /soc@0/bus@30800000/i2c@30a40000/i2cmux@70/i2c3: node has a reg or ranges property, but no unit name
Serge Semin [Mon, 8 Feb 2021 13:51:45 +0000 (16:51 +0300)]
ARM: dts: ls1021a: Harmonize DWC USB3 DT nodes name
In accordance with the DWC USB3 bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly
named.
Dima Azarkin [Sun, 31 Jan 2021 15:54:46 +0000 (18:54 +0300)]
ARM: dts: imx6qdl-wandboard: add scl/sda gpios definitions for i2c bus recovery
The i2c bus on imx6qdl-wandboard has intermittent issues where SDA can freeze
on low level at the end of transaction so the bus can no longer work. This
impacts reading of EDID data leading to incorrect TV resolution and no audio.
This scenario is improved by adding scl/sda gpios definitions to implement the
i2c bus recovery mechanism.
For now, the driver detects an incompatible version, but since
that can be handled by auto-detection, add the controller to the
devicetree now. Only PWM seems to be available, there is no RTC
in that controller.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable the Netronix EC on the Kobo Aura ebook reader.
Several features are still missing:
- Frontlight/backlight. The vendor kernel drives the frontlight LED
using the PWM output of the EC and an additional boost pin that
increases the brightness.
- Battery monitoring
- Interrupts for RTC alarm and low-battery events
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
projects / users / jedix / linux-maple.git / log